Vinodkumar SS

Software Engineer

Bengaluru, Karnataka, India9 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in design verification methodologies and tools.
Proven track record in FPGA subsystem verification.
Strong debugging skills with industry-standard tools.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in design methodologies.

Contact

vinodkumarss36@gmail.com LinkedIn

Skills

Core Skills

Functional VerificationUniversal Verification Methodology (uvm)FpgaDebug

Other Skills

verilogSystemVerilogAssertionsCoverage AnalysisVerdiCode CoverageConstraintsBug TrackingDVEJiraVCSStatic Timing AnalysisMicrosoft OfficeMicrosoft WordCustomer Service

About

Design Verification Engineer with experience in IP, Subsystem and SOC level verification. Successfully applied Verilog, SystemVerilog, UVM and Synopsys tools (Verdi, DVE) to efficiently verify, identify and resolve design issues, ensuring delivery of robust, high-quality designs. When I’m not verifying designs, you can find me planning my next travel destination, playing badminton or carrom or chess, else hitting the trails for a hike or a long bike rides.

Experience

9 yrs 8 mos

Total Experience

1 yr 6 mos

Average Tenure

3 yrs 1 mo

Current Experience

Google

Design Verification Engineer

May 2023 – Present · 3 yrs 1 mo · Bengaluru, Karnataka, India · Hybrid

Functional VerificationverilogSystemVerilogUniversal Verification Methodology (UVM)AssertionsCoverage Analysis+4

Einfochips (an arrow company)

Senior Verification Engineer 1

Jan 2023 – May 2023 · 4 mos · Bengaluru, Karnataka, India · Hybrid

Integration of I2C VIP.
TB and testcases development.

Tessolve

Design Engineer

Jul 2021 – Jan 2023 · 1 yr 6 mos · Bengaluru, Karnataka, India

Client: Intel Bangalore
● Working in FPGA Subsystem verification involving PLL, GPIO and IOLVDSRX.
● Created test cases using RBC (Rules Based Constraints) for connectivity checks and
updated tb for the individual tests of GPIO, IOPLL and LVDS RX blocks.
● Updated sequences for IP test cases and coverage files.
● Involved in debugging DDR test cases at subsystem level and updated for specific
features.
● Engaged in coverage merge and updated a legacy perl script for merging coverage of
multiple test cases/regressions and generating reports as per date.
● Formulated a report of coverage progress, coverage holes as per the date in excel sheet
and delivered detailed information.

FPGASystemVerilogConstraintsCoverage AnalysisDVEUniversal Verification Methodology (UVM)+1

Amd

Verification Engineer (Contractor)

Oct 2018 – Jul 2021 · 2 yrs 9 mos · Bengaluru, Karnataka, India · Hybrid

● Performed in a central debug team of AMD Processor SoC.
● Involved in debugging test cases with different signatures.
● Familiar on tools like Jira and Synopsys VCS.
● Have a basic knowledge on Computer Architecture.

DebugJiraBug TrackingFunctional VerificationVCSCoverage Analysis+3

Smartsoc solutions pvt ltd

Verification Engineer

Aug 2018 – Jul 2021 · 2 yrs 11 mos · Bengaluru Area, India

SmartSoc acquired Insilico Techservices in the month of June 2019.

Synopsys ind pvt ltd

Techincal Intern/IP Verification Engineer

Oct 2017 – Jul 2018 · 9 mos · Bengaluru Area, India

● Worked on DDR5 PHY interface solution used to provide physical interface to standard
DDR5 memory.
● My work involved DDR PHY sideband feature verification and verification infrastructure
improvement.
● Worked on DFI (DDR Physical Interface) involving sideband feature verification of
PHY-Master interface and a part of Frequency change mechanism.
● The sideband verification involved the collisions between PHY-Master interface,
Low-Power mode, Control Update and frequency change.
● Involved in writing/updating test cases to verify sideband features/scenarios, updating
checkers, writing functional coverage and running regressions.
● Performed debugging and resolved the issues in testbench, sequences and checkers.