Yashodhan Srivastava

Software Engineer

Delhi, India5 yrs 10 mos experience

Key Highlights

  • Experienced FPGA Engineer with strong hardware design skills.
  • Proficient in Static Timing Analysis and Digital Circuit Design.
  • Hands-on experience with Verilog and FPGA implementations.
Stackforce AI infers this person is a Semiconductor Engineer with expertise in FPGA and hardware design.

Contact

Skills

Core Skills

Hardware EngineeringStatic Timing AnalysisDigital Circuit Design

Other Skills

AMBA APBAbleton LiveAnalog CircuitsArduinoAutomatic Test Pattern Generation (ATPG)C++CDCCadence VirtuosoCircuitsComputer HardwareDFTDigital ElectronicsElectronic Circuit DesignElectronicsEmbedded C

About

FPGA Engineer at Mathisys Former STA Engineer at Qualcomm Former Product Validation Engineer 1 at Cadence Design Systems | DFT Former R&D Engineer, FPGA at QBit Labs Private Limited Former intern at Samsung Semiconductor India Research

Experience

Mathisys

FPGA Engineer

Dec 2024Present · 1 yr 3 mos · Gurugram, Haryana, India · On-site

Qualcomm

STA Engineer

Jul 2022Dec 2024 · 2 yrs 5 mos · Noida, Uttar Pradesh, India

Hardware EngineeringProblem SolvingSynopsys PrimetimeStatic Timing Analysis

Cadence design systems

2 roles

Product Validation Engineer 1

Jun 2021Jul 2022 · 1 yr 1 mo · Noida, Uttar Pradesh, India

Hardware EngineeringProblem Solving

Trainee (Product Validation)

Mar 2021Jun 2021 · 3 mos · Noida, Uttar Pradesh, India

Hardware EngineeringProblem Solving

Qbit labs private limited

R&D Intern

Jan 2021Mar 2021 · 2 mos · Gurugram, Haryana, India

Hardware EngineeringProblem Solving

Samsung electronics

Summer Intern

May 2020Jul 2020 · 2 mos · Bengaluru, Karnataka, India

  • Summer Intern at Samsung Semiconductor India Research, Bangalore
Hardware EngineeringProblem Solving

3st technologies

Trainee

Dec 2019Jan 2020 · 1 mo · Noida, Uttar Pradesh, India

  • Winter Training, 3ST Technologies, NOIDA
  • VLSI: Digital Design, Static Timing Analysis, Verilog HDL, FPGA
  • ▪ 16th December 2019 to 24th January 2020
  • ▪ Projects: UART Design Using Verilog HDL
  • ▪ Description: Gained knowledge about the concepts mentioned above and implemented various Verilog designs on Xilinx BASYS2 FPGA.
Problem Solving

Unmanned ground vehicle dtu

Vice Captain

Aug 2019Jun 2020 · 10 mos · Delhi, India

Hardware EngineeringProblem Solving

Education

Delhi Technological University (Formerly DCE)

Bachelor of Technology - BTech — Electronics and Communications Engineering

Jan 2017Jan 2021

The Army Public School, Dhaula Kuan, New Delhi

Jan 2017Present

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