Parmeet Singh — Software Engineer
Design Engineer at Siemens EDA, Noida, India. Specialties: RTL Design, VHDL, Verilog, FPGA design & architecture, RTL coding, Simulation, Synthesis, PCIe, FPGA Complete Flow, other includes - Hybrid Computing Systems, Ethernet, Automotive.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in FPGA and digital design.
Location: Noida, Uttar Pradesh, India
Experience: 15 yrs 6 mos
Skills
- Rtl Design
- Fpga Design
Career Highlights
- Expert in RTL Design and FPGA architecture.
- Proficient in high-speed digital design and timing closure.
- Strong background in PCIe and hybrid computing systems.
Work Experience
Siemens EDA (Siemens Digital Industries Software)
Design Engineer (7 yrs 5 mos)
NEC India
Technical Lead (2 yrs 5 mos)
SMTS (2 yrs 3 mos)
Mando Corp.
Senior Engineer (1 yr 7 mos)
Center for Development of Advanced Computing (CDAC) R&D, Pune
PE (1 yr 10 mos)
Education
Master of Science - MS at Indian Institute of Technology, Delhi
PG Diploma at Advance Computing Training School,CDAC, Pune, India
Engineer's degree at IETE, Delhi, India
