Feb 2018 – Jan 2020 · 1 yr 11 mos · Austin, Texas Area

• Functional Verification – L2 Cache Controller
• Responsible for functional verification of L2 cache controller for a state-of- the-art ARM based CPU.
• Responsibilities include development and execution of verification strategy, test-bench architecture and test-plan.
• Development of test bench components like Monitor, Scoreboard, Test sequences and Tests using System Verilog and UVM.
• Interfacing with chip architects and designers for design review, integration and bug fixes.
• Functional and Code coverage closure.

May 2017 – Aug 2017 · 3 mos · Austin, Texas Area

• Part of Test bench and VIP development team
• Developed functional tests for pad testing (level tests, hiz and pullup/down tests) of an audio amplifier chip and attained 100% functional coverage with coverage plan designed for extensive coverage.
• Developed a reusable and scalable verification IP in UVM environment, which can be used for pad testing of all Cirrus products.

Aug 2016 – Dec 2017 · 1 yr 4 mos · Raleigh-Durham, North Carolina Area

Jul 2013 – Jul 2016 · 3 yrs · Bangalore

• RTL development for FPGA’s: Design, Pin Assignment, Implementation, Verification, Static Timing Analysis and target testing of Control FPGA’s.
• Implementation of Control Card functionalities like Clock distribution, reset generation and interrupt handling etc. in the Control FPGA and the interfaces needed to control all other tributary cards like LPC, I2C etc. in a network node.
• Design and Implementation of Interrupt generation scheme for early power down condition and early jack out of the card.
• Implemented timing and synchronization scheme in the Control Card for synchronization of the system.
• Worked on design and implementation of control byte extraction from OTN frame, unwrap HDLC format and wrap the bytes into Ethernet format for transferring to processor.
• Solved critical issues related to implementation and timing issues of control FPGA on multiple cards.
• Worked on Xilinx Spartan 6 FPGA family FPGA’s and got familiar with the architecture.
• Skills used/improved/acquired: Verilog programming, C programming, Shell scripting, Schematic design and review.
• Design/Development tools used: Xilinx – ISE, Cadence – Allegro tools, Cadence – NCSim, Aras – Innovator

Jul 2012 – Dec 2012 · 5 mos · Bengaluru Area, India

• Developed a program using Perl for automating measurement of Component Video Parameters on an instrument VM5000 which increased the video testing time efficiency by 70%.
• Developed a tool using Perl for automating measurement of Composite Video Parameters on an instrument VM700T which increases the video testing time efficiency by 90%.
• Skills used/improved/acquired: Perl scripting, Cross component interfacing and communication protocols (GPIB).