Mohit Sharma — AI Researcher

Experienced VLSI Front-End Engineer specializing in FPGA & ASIC designs verification with expertise in Verilog, VHDL, System Verilog, UVM, and Matlab Simulink. Skilled in Simulation, Emulation and Formal Verification to ensure Functional Correctness & Performance optimization along with the strong expertise in verification automation, testbench development and debugging complex digital design. Contributing to High Quality & Reliable VLSI designs. My skills include: • Development of Automated Self-Checking UVM based test-bench using Assertions, Functional Coverage and Constraint Randomisation techniques • HDL Co-Simulation, Simulink FIL & Hardware Assisted verification using Emulators • Experience in generating corner cases and un-anticipated test scenarios for complete verification ensuring there are no bugs in the design • Static and Dynamic Code Analysis: CDC, RDC, RTL Linting checks, Formal Analysis and Equivalence checking • Synthesis constraints, Timing Simulations & Static Timing Analysis (STA) • Hands-on experience in HDL (VHDL and Verilog) and HDVL (System Verilog) • Strong expertise in Digital System Designs and RTL development

Stackforce AI infers this person is a VLSI Front-End Engineer specializing in FPGA and ASIC design verification.

Location: Ahmedabad, Gujarat, India

Experience: 7 yrs 9 mos