T

Thuppala Ranga

Software Engineer

Bengaluru, Karnataka, India5 yrs 11 mos experience
Highly Stable

Key Highlights

  • Senior Design Verification Engineer with extensive RTL expertise.
  • Proficient in UVM and functional verification methodologies.
  • Strong background in digital electronics and design verification.
Stackforce AI infers this person is a Design Verification Engineer with expertise in RTL and functional verification in the semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

Rtl VerificationFunctional Verification

Other Skills

VerilogUniversal Verification Methodology (UVM)PerlDigital ElectronicsRTL Design

Experience

5 yrs 11 mos
Total Experience
5 yrs 11 mos
Average Tenure
5 yrs 11 mos
Current Experience

Mediatek

2 roles

Senior Design Verification Engineer

Promoted

Jul 2024 – Present · 1 yr 9 mos

VerilogUniversal Verification Methodology (UVM)RTL VerificationPerlDigital ElectronicsFunctional Verification+1

Design Verification Engineer

May 2020 – Jul 2024 · 4 yrs 2 mos

Education

JNTU Anantapur

Bachelor of Technology - BTech — electronics and communication engineering

Jan 2015 – Jan 2019

sree chaitanya junior college,vijayawada

inter — MPC

Jan 2013 – Jan 2015

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