Dec 2023 – May 2024 · 5 mos · Bengaluru, Karnataka, India · On-site

Jun 2021 – Dec 2023 · 2 yrs 6 mos · Bengaluru, Karnataka, India

• ASIC RTL Design, Low Power Design, CPUSS Sub-System, ARM Arch, System Debug, Post-Si Debug.
• CPUSS Design Engineer primarily focused on the Low power design (Active and Idle power management).
• Scenario based Clocking Analysis and impact to power across different use-cases. Strong understanding of Power/Performance modes, DCVS (Dynamic Clock Voltage Scaling) techniques and their implications to Power & Performance
• Extensive interaction with Cross Functional Teams such SoC Engineering, SW Leads, Worldwide IP Core teams, Product/Test Engineering etc. - analyzing PPA tradeoffs, HW/ SW interfaces, and re-usability of various IPs/ Cores
• Worked on Design & Integration of ARM's Cortex A53/A57 based Application Processor Sub-Systems for Premium Tier chipsets.
• Define and design various Core, L2/L3 and Sub-System level low power modes.
• Publish SW steps and HW sequences for entry/exit for various LPM.
• Familiar with Analog block integration (Current Sensors/Voltage Sensors/Temp Sensors, PLL’s).
• Good Understanding of DFT/DFD(Scan/JTAG/TAP)
• Good at Pre/Post Silicon Debug’s
• Good at Spyglass Design Linting/CDC and Conformal CLP UPF flows

Sep 2018 – Jun 2021 · 2 yrs 9 mos · Bengaluru Area, India

• SoC DRAM Memory Sub-System Intel Arch, Low Power Design, System Debug, Post-Si Debug
• Designed Interconnect ARM to Intel Arch compliance and vice versa
• Worked on power and performance optimization of Intel Memory Sub Systems
• Debugged several system level Pre-Silicon and Post-Silicon issues for Intel Client SoC's
• Worked on power and performance optimization of Intel processors for servers and clients.
• Debugged several Pre-Silicon issues.

Jan 2017 – Sep 2018 · 1 yr 8 mos · Bengaluru Area, India

•  Worked in DRAM memory research team in prototyping and validating new features like security
• in dram and processing in memory for next generation memories for Samsung.
• Granted US patent (20200341775) for security feature design for dram.
•  RTL Design and prototyping is done on Xilinx FPGA.
•  Performed Timing Analysis and validated the designs on FPGA board. Debugged the system
• failures and successfully prototyped the DRAM features.
•  Emulated NVDIMM-P memory controller PHY design and implementation on Xilinx Fpga.

Mar 2015 – Jan 2017 · 1 yr 10 mos

• Worked in Designing DDR4/3 High Speed PHY for Xilinx External Memory Interfaces.
• Used processor-based system for calibrating Memory and expert on usage of Micro blaze-based systems.
• Timing Analysis and debug of Memory IP designs with Vivado tool.
• Extensively used and had very good understanding on Xilinx Debug IP's (ILA, VIO Cores).
• Debugged and Fixed Several Design Issues and found key corner Silicon bugs.
• Expert in all Debugging with Verification, Simulation, Hardware tools.
• Very Good knowledge on using High end Oscilloscopes for hardware debugging and probing.
• Done Emulation of Xilinx 7nm NoC and Memory Controller designs.
• Validation of Memory designs at IP, sub system and system level.
• Developed fully Automated Hardware Validation Platform which was remote and scalable for all Xilinx Memory IPs for FPGA's.
• Automation framework for varying input vectors to validation platform like, system clock sweep, voltage variations and Temperature variations.

Jul 2012 – Mar 2015 · 2 yrs 8 mos