vipin kumar — Product Engineer

12+ Years of experience in VLSI domain on IP/SoC Verification • Currently working as Senior Lead Design Engineer at NXP Semiconductor Pvt. Ltd. Noida • Lead/Managed Verification of Automotive IP’s from last 5 Years. • Define the ISO26262 Fault Injection Methodology and deploy on Automotive IPs and signoff the fault coverage based on ASIL level. • Have lead verification team of medium size for multi-million gate IP verification from scratch • With Complete ownership as Verification lead have done multiple IP signoff • Expertise in doing verification archerite for multi-million IP from Debugging ease till the coverage closure • Have insight on formal verification, have used formal in sub-blocks • For Achieving Zero defect and 1st time Success criteria, our IP environments focus from all the angles, like +ve feature testing, Stress testing, negative/error scenarios & performance verification • Based on Root Cause Analysis (RCA) of older devices bugs have done multiple enhancement in our verification environment flow • In-depth understanding of Radar and Vision IP’s • Expertise in UNR flow. With use of UNR signed off an IP with 100% coverage where simulation coverage was not going beyond ~60% • Modeling of bridges between Proprietary bus of IDS and AMBA-AXI, AMBA-APB, AMBA-AHB, AMBA3-AHBlite. • Created the UVM Register Model guidelines. • I have worked extensively on various verification methodologies like Simulation based verification using traditional Verilog bases to System verilog based testbenches, from custom system verilog based to standard UVM based verification environment and Coverage Driven Verification as well. HDL: Verilog and VHDL HVL : System Verilog Platforms: Linux, Windows Verification Frameworks: UVM Tools:Mentor Graphics: ModelSim, QuestaSim Synopsys: VCS, DVE Cadence: NC Verilog, SimVision, Incisive Popular standards and buses:AMBA AXI, AMBA-AHB, AMBA3-AHBlite, AMBA-APB, PCIE Specialties: Verilog, System Verilog, UVM BLOG/ARTICLES PUBLISHED 1. Blog “Questa® VIP validates IDesignSpec generated IP” published on the company website. 2. Articles “QVIP provides thoroughness in verification” published in verification horizon.

Stackforce AI infers this person is a VLSI Verification Engineer with expertise in automotive IP verification.

Location: Delhi, India

Experience: 14 yrs 9 mos