Shamakumar P.

DevOps Engineer

Bengaluru, Karnataka, India9 yrs experience

Key Highlights

Expert in SoC validation and embedded software development.
Led critical projects in automotive functional safety.
Proficient in multiple programming languages and tools.

Stackforce AI infers this person is a highly skilled Automotive Validation Engineer with expertise in embedded systems and functional safety.

Contact

Skills

Core Skills

Silicon ValidationFunctional VerificationFirmwareDevice Drivers

Other Skills

ARM Cortex-MAdvanced Driver-Assistance Systems (ADAS)Agile MethodologiesApplication-Specific Integrated Circuits (ASIC)Assembly LanguageBit BucketBoard Bring-upC (Programming Language)C++DockerEB TresosEmbedded CEmbedded SystemsEnterprise ArchitectGNU debugger

About

Post silicon Validation Engineer, Team Lead Experienced, with a background in SoC validation (functional and electrical), Experienced in Embedded software development lifecycle specialised in Automotive functional safety security domine R&D, worked in Critical projects as verification and validation Engineer for multiple IP's Including ASIL-D to QM components. Languages/Framework: Embedded C, Assembly, Python, Perl, JSON, Powershell. Others: Lauterbach Trace32, Docker, Enterprice Architect, JIRA, EB Tresos, GNU debugger. Version Control: Git, Gerrit, IBM clear case, Bit Bucket.

Experience

Qualcomm

Senior Lead Engineer

Dec 2024 – Present · 1 yr 3 mos · Bengaluru, Karnataka, India · Hybrid

Intel corporation

Post Silicon Validation Engineer

May 2022 – Nov 2024 · 2 yrs 6 mos · Bengaluru, Karnataka, India

1. CPU-Subsystem Verification and Validation.
o Boot-up multicores ARM M0, M7, R5 and SI (Safety Island) R5.
o Verify signals and TRACE32 to validate TCM memory access of different cores.
o Enable and validate system control access for different peripherals.
o Enable and validate FuSa, Memory (SRAM), Interrupt access.
o Enable and validate IPC communication between al the Cores.
2. OTP-eFuse Verification and Validation.
o Validate Fuse Sensing from APB and JTAG interfaces.
o Validate Security and Locking mechanism from Fuse Controller.
o Design and Validate Fuse Overriding.
o Design and Validate Fuse Distribution.
o Validate TAP and CLTAP after Fuse Overriding.
3. GIC and NVIC Verification and Validation.
o Enable and Configure Interrupt handlers (GIC & NVIC) for functional validation.
o Set, Prioritize, Configure and Clear IRQ’s for all the Cores.
o Configure NVIC interrupt handlers for M0 and M7.
o Configure GIC interrupt handlers for R5 and SI_R5.
o Design Vector table for functional validation.

ARM Cortex-MBoard Bring-upSilicon ValidationAssembly LanguageTrace32Functional Verification+8

Nxp semiconductors

V&V/Test Engineer - II

Jul 2021 – Apr 2022 · 9 mos · Bangalore Urban, Karnataka, India

1. Radar Front End Digital Smart Trans Receiver Clocking Design and Validation(ARMv7).
o Requirement analysis from DOORS for different Cores and Partition for CM_7 and A53.
o System initialization with different clock configurations during BOOT and ACTIVE mode.
o Design and Validation of clock generation module (VCO, PLL, MUX & DIVIDER configurations).
o Design and Validation of clock monitoring Units for multiple clock sources.
2. Radar Front End Digital Smart Trans Receiver RESET Design and Validation(ARMv7).
o Requirement analysis from DOORS for different Cores and Partition for CM_7 and A53.
o RESET sequence generation for entire silicon.
o Design and Validation of RESET generation module.
o Monitoring RESET based on Fault collection control unit inputs.
3. Radar Front End Digital Smart Trans Receiver POWER Design and Validation(ARMv7).
o Requirement analysis from DOORS for different Cores and Partition for CM_7 and A53.
o LOW Power run mode ACTIVE mode design and validation.
o Monitoring Critical and Non Critical faults and Supply presence detection.
o Supply configurations for multiple IP’s.
4. Radar Front End Digital Smart Trans Receiver Repository.
o Creating new repository for the project and node in BitBucket
o Setting up of VISTA/NOVA Compilation environment.
o Update CMM and Environmental script files and bash files.
o Updating Startup code and header files and memory map files for the repository.
o Configuring IO-MUX files.
5. Zebu Bring-UP.
o Creating new Pre silicon XML files.
o Updating CMM and environmental scripts.
o Setting up of Emulation environment.
o Configuring Lauterbach and Trace-32.
o Creating execution platform.

Functional VerificationARM Cortex-MUniversal Asynchronous Receiver/Transmitter (UART)FirmwareDevice DriversBoard Bring-up+8

Robert bosch engineering and business solutions private limited

Senior Software Engineer

May 2019 – Jun 2021 · 2 yrs 1 mo · Bangalore

1. MCAL Driver Development/Validation for AURIX Controllers.
o Requirement Analysis of MCAL(AUTOSAR) drivers.
o Development of Reset Control Unit and Power Management Unit drivers for Aurix controller. Performing Extended Flash test validation and Robustness check.
o Review of Software Architecture Specification.
o Development of Integration test specification and Software test specification.
o Development of test cases for MCU (Clocking IP, Reset IP, Trap IP, Power IP), STM-timer, Watchdog driver.
o Development of test cases for multicore, multi-partition architecture.
o Development of test environment.
o Participate in defect analysis.
o Code review.
2. Electronic Breaking System (EBS)
o Development of automation tool for extraction of assembly code from list files for compiler validation team..
o Development of automation tool for the generation of compiler validation report which helped in reducing the manual effort for compiler validation team.
o Development of test environment for the validation team.
o Test driven development or Validation of braking system software for Safety related components(ASIL-D driver).
o Complete Ownership – Concept, Requirements, Design, Testing and Integration.
o Validation of Low Level Drivers software in software-in-loop based testing(ASIL-D).
o Interaction with counterparts for project related clarifications and status updating.
3. UML model Implementation for AUTOSAR components
o Performed Requirement based model designs for more than 12 components.
o Implemented Static and Dynamic behaviors of the components interacting in different layers.
o Auto and manual generation of interfaces, attributes and operation of safety related components.
o Encapsulated program flow in alignment with the software and customer requirements.

FirmwareDevice DriversAssembly LanguageApplication-Specific Integrated Circuits (ASIC)LinuxRequirements Analysis+3

Infineon technologies

Software Engineer

Dec 2017 – Apr 2019 · 1 yr 4 mos · Bangalore

The Automated Regression Test Infrastructure is developed for the resource management and efficient testing of Infineon Aurix series of microcontrollers under the conventional test tool UVP and integration of NI PXI hardware with Labview. (For IPs including CAN, QSPI, PWM, etc…).
Aurix and Aurix 2G Automotive MCAL Driver validation for different IPs.
Worked on Software development and validation infrastructure improvement for different projects like MCAL, Safety Libraries and Secure Hardware.
Worked on Integrated validation environment using C-Model and Virtual Prototyping.
Worked on prototyping fault injection using C-Models and SimProbe (from Synopsis) for enabling software validation by removing actual silicon and hardware dependency.
Worked on RnD topics to evolve Continuous Integration and Validation topics using Jenkins, Perl and other software development tool chains.
Worked on WCET (Worst case Execution Timing Analysis of APIs) infrastructure development (to enable Automotive MC Low Level Driver Development) using Rapitime from Rapita Systems Gmbh.
Worked on Automated unit testing infrastructure development (to enable Automotive MC Low Level Driver Development) using Tessy (TestSystems) from Razorcat Gmbh.

Universal Asynchronous Receiver/Transmitter (UART)FirmwareDevice DriversBoard Bring-upAssembly LanguageApplication-Specific Integrated Circuits (ASIC)+6