Kshitij Bajaj

CTO

Noida, Uttar Pradesh, India23 yrs 7 mos experience

Highly Stable

Key Highlights

Expert in SoC design and architecture optimization.
Delivered multiple Radar and Vision subsystems.
Holds 11 patents in graphics and safety applications.

Stackforce AI infers this person is a Semiconductor expert specializing in SoC design and validation for Radar and Vision applications.

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Skills

Core Skills

Soc DesignArchitectureRadarVisionFpga DesignSecurityAutomation

Other Skills

ADAS algorithmsAESAES encryptionASICATPGApplication-Specific Integrated Circuits (ASIC)DESDFTDebuggingFPGA validationField-Programmable Gate Arrays (FPGA)Functional VerificationHardware DevelopmentHashingIP design

About

SoC Design Lead for next gen SoC development at Renesas. Previously worked for the next generation Radar designs (S32R Family) at NXP. Focus on optimizing IP/SoC Architectures meeting customer requirements in the most advanced technology nodes. Working closely with Systems, Architecture & SW teams across geographies in realizing the most optimal designs. Successfully delivered multiple subsystems in the field of Radar/Vision including end to end verification and performance signoffs. Involved in all Front end activities including IP design, IP verification, SOC verification and validation both at pre & post Silicon. Specialties: SoC design, Architecture IP design, Pre and post silicon validation, FPGA design flow, Graphics standards, low power GPU, Video Standards, Vision, Radar, ADAS, Cluster, Display, Video Compression 11 Issued patents in the field of graphics/displays/safety/vision applications. Multiple publications in the field of low power and methodologies for reducing power consumption at IP level.

Experience

Renesas electronics

Distinguished Engineer

Jun 2024 – Present · 1 yr 9 mos · Noida, Uttar Pradesh, India · On-site

Nxp semiconductors

Technical Director

Jun 2005 – Jun 2024 · 19 yrs · Noida Area, India

Broad experience in working with global teams in delivering IP's and subsystems for multi million devices targeted for Radar , Vision, Driver Information Systems and safety applications. Working closely with customers for evaluation and development of architectures to solve the current challenges in delivering real time performance for NXP Vision and Radar based devices. Good knowledge on ADAS algorithms both in Radar and Vision domain and partitioning of algorithm tasks between various accelerators to optimize device performance.
Involved in end to end delivery of Digital IPs including development of specifications,developing micro architecture for the requirements, RTL coding, Implementation for successful IP release.Supporting pre Silicon validation on FPGA/Palladium and post Silicon validation teams verifying IP functionality.
Broad experience in the architecture/design of following
Display Controllers
Video Interfaces
JPEG Encoder/Decoders
Image Signal Processors - programmable/hardwired
GPUs
HW accelerators for Radar signal processing
Image Rectification
Stereo Disparity
Optical Flow

IP designsubsystems deliveryarchitecture developmentRTL codingpre Silicon validationpost Silicon validation+2

Samsung electro mechanics india pvt ltd bangalore

Design Engineer

Jun 2004 – Jun 2005 · 1 yr · Bengaluru Area, India

Design and development of AES encryption standard in VHDL

VHDLAES encryptionFPGA design

Bisquare technologies delhi

Member Technical Staff

Jul 2003 – Aug 2004 · 1 yr 1 mo · Delhi

1) Involved in design Security IP's and related algorithms like DES,AES,Hashing etc.
2) After RTL coding porting the design on Xilinx FPGA and validating the IP functionality

Security IP designFPGA validationSecurity