Jigar Patel — Software Engineer

Excellent Knowledge in Memory Layout Architecture Design. Excellent Knowledge in ASIC Design Flow and Full Custom Flow. Have a experience in memory compiler like SRAM, ROM, RF and Standard cell design in various technology nodes : 2nm 3nm 4nm 5nm 7nm 14nm 22nm Finfet , 22nm FDSOI, 28nm Bulk Cmos. Works on Various blocks like Bitcell, Sense Amp, I/O cell, Control and Decoder. Excellent Skill to debug DRC, LVS, ERC, DFM, Density, EM/IR issues. Good knowledge of cadence skll coding for layout automation. Hands on experience with Cadence Virtuoso, Synopsys Custom Compiler, Voltus-fi and Mentor Graphic Calibre. Concise understanding of logic design and CMOS concepts.

Stackforce AI infers this person is a VLSI design expert specializing in ASIC and memory layout architecture.

Location: Bengaluru, Karnataka, India

Experience: 11 yrs 1 mo