Dhavala Bhat

Product Engineer

Dallas, Texas, United States2 yrs 8 mos experience

Most Likely To Switch

Key Highlights

Led RTL code development for 5G Testbed Project.
Automated communication setup reducing time by 40%.
Skilled in ASIC design and digital verification.

Stackforce AI infers this person is a Telecommunications ASIC Design Engineer with expertise in digital design and verification.

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Skills

Core Skills

Asic DesignRtl DevelopmentDigital Design Verification

Other Skills

5G TechnologyAnalog CircuitsAnalog Integrated Circuit DesignApplication-Specific Integrated Circuits (ASIC)Artificial Neural NetworksArtix - 7 FPGACC (Programming Language)Cadence GenusCadence InnovusCadence VirtuosoCadence Virtuoso Layout EditorCadence innovusClock Tree SynthesisCollaborative Problem Solving

About

Passionate Specialist with hands-on in ASIC design and the related fields. Skilled in Front-end (RTL) Design, Back-end (Physical) Design, Digital Design (specialist), FPGA, Verilog, VHDL and C. Completed Master of Science (MS) specialized in VLSI Design from The University of Texas at Dallas, USA. As a ASIC Design Engineer at IISc, my contributions to the 5G Testbed Development Project of India were significant, leading RTL code development and automating communication between devices. We developed a Python-based interface, cutting setup time by 40%, showcasing my proficiency in hardware design and computer architecture.

Experience

2 yrs 8 mos

Total Experience

1 yr 4 mos

Average Tenure

1 yr 10 mos

Current Experience

Kgs

Physical Design Engineer

Jun 2024 – Present · 1 yr 10 mos · United States · Remote

Indian institute of science (iisc)

Research Associate

Sep 2021 – Jul 2022 · 10 mos · Bengaluru, Karnataka, India · On-site

I was a part of the Core Network team in the 5G Testbed Development Project of India.
Led the ASIC code development for Radix-4 Booth Recoded Multiplier using Verilog and full RTL to GDS flow including physical design and debugging using Cadence Genus and Innovus for the Core Network
Improvised a C programming script to automate communication between Base Station and User Interface, enhancing system efficiency.
Developed a Python based User Interface automating the setup of power, frequency and other parameters of a frequency synthesizer, resulting in approximately 40% reduction in setup time.

VerilogRTL to GDSII FlowCadence GenusCadence InnovusCPython+2

Capgemini

Digital Design Verification Intern

Jan 2021 – Apr 2021 · 3 mos · Bengaluru, Karnataka, India

Collaborated with a team of 5 in designing and developing a Python-based mobile app to automate bus ticket booking.
Deployed the customer feedback module in the app to acknowledge customer satisfaction via ratings and comments.

PythonMobile App DevelopmentDigital Design Verification

Leoch batteries india pvt ltd

Intern

Jun 2019 – Aug 2019 · 2 mos · Bengaluru, Karnataka, India

Learnt few concepts about the battery design, battery manufacturing and got hands-on experience with the recharging
and discharging of the lead acid batteries.