Raghu Reddy

Software Engineer

Bengaluru, Karnataka, India13 yrs 9 mos experience
Highly Stable

Key Highlights

  • Experienced in ASIC design and engineering.
  • Proficient in Static Timing Analysis and scripting languages.
  • Strong background in VLSI systems from a reputed institution.
Stackforce AI infers this person is a VLSI design engineer with expertise in ASIC development.

Contact

LinkedIn

Skills

Other Skills

asic designStatic Timing AnalysisTCLPerl

Experience

13 yrs 9 mos
Total Experience
4 yrs 1 mo
Average Tenure
1 yr 5 mos
Current Experience

Broadcom

Staff Engineer

Nov 2024 – Present · 1 yr 5 mos · Bengaluru, Karnataka, India

Intel technologies india

Staff Engineer

Dec 2017 – Nov 2024 · 6 yrs 11 mos · Bengaluru, Karnataka, India

  • ASIC DESIGN ENGINEER

Mediatek

Senior Design Engineer

Jun 2015 – Dec 2017 · 2 yrs 6 mos · Bangalore

Lsi corporation

ASIC DvDs Engineer

Jul 2012 – Jun 2015 · 2 yrs 11 mos · Bangalore

Education

National Institute of Technology, Tiruchirappalli

Master of Technology (M.Tech.) — VLSI SYSTEMS

Jan 2010 – Jan 2012

Stackforce found 100+ more professionals with asic design & Static Timing Analysis

Explore similar profiles based on matching skills and experience

Sai Seshagiri Rao B V

Sai Seshagiri Rao B V

Senior Staff Engineer

at MediaTek

Bengaluru, India14 yrs 4 mos exp
Physical VerificationPhysical Design
Ankush Chaudhary

Ankush Chaudhary

Senior Engineer

at MediaTek

Wardha, India2 yrs 9 mos exp
Application-Specific Integrated Circuits (ASIC)Synthesis
Sumanth Babu Lavanuru

Sumanth Babu Lavanuru

Physical Design Engineer

at Intel Corporation

Bengaluru, India7 yrs 9 mos exp
Physical DesignTiming Closure
Suresh kola

Suresh kola

SMTS Silicon Design Engineer

at AMD

Bengaluru, India15 yrs exp
Physical DesignASICSoC
Avilash Mohanty

Avilash Mohanty

Senior Physical Design Engineer

at NVIDIA

Delhi, India8 yrs 9 mos exp
Arun Koithyar

Arun Koithyar

Digital Design Manager

at Texas Instruments

Bengaluru, India25 yrs 2 mos exp
R.

Ritika ..

Staff Engineer

at Qualcomm

Delhi, India15 yrs 5 mos exp
Physical DesignTiming Closure
Jnana Phaneendra

Jnana Phaneendra

Contractor

at AMD

Hyderabad, India4 yrs 5 mos exp
Physical Design