Mohammad Safiullah

CTO

San Francisco, California, United States21 yrs 8 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Architected and developed over 9 IPs for telecommunications.
  • Proficient in ASIC and FPGA design.
  • Strong experience in micro architecture and RTL development.
Stackforce AI infers this person is a Telecommunications ASIC and FPGA design expert with extensive experience in IP development.

Contact

LinkedIn

Skills

Core Skills

TelecommunicationsAsicFpga

Other Skills

Micro Architecture designRTL developmentCoordinationDigital ASIC designOIF-SAR standardFPGA ImplementationHDLC Over PCI-ExpressCircuit Emulation IPEthernet Over PDHEthernet Over HDLCE1/T1/E3/DS3 signal mappingSDHEthernetVerilogC

About

• Experienced ASIC & FPGA designer • Proficient in modelling algorithms in Matlab/C • Proficient in architecture & micro architecture design from functional specifications • Architected & Developed 9+ IPs for Telecommunications and Networking applications

Experience

Cisco

4 roles

Technical Leader

Apr 2022 – Present · 3 yrs 11 mos

Technical Leader

Promoted

May 2018 – Apr 2022 · 3 yrs 11 mos

  • Architecting IPs for Telecommunication and Networking applications from system specifications
  • Micro Architecture design and RTL development
  • Co-ordination between different ASIC functions
TelecommunicationsMicro Architecture designRTL developmentCoordinationASIC

ASIC Engineer IV

Dec 2014 – Apr 2018 · 3 yrs 4 mos

  • Design and development of digital ASICs for Telecommunication/Computer Networking applications
  • Co-ordination between different ASIC functions
Digital ASIC designTelecommunicationsCoordinationASIC

ASIC Engineer III

Apr 2013 – Nov 2014 · 1 yr 7 mos

  • Design and development of digital ASICs for Telecommunication/Computer Networking applications
Digital ASIC designTelecommunicationsASIC

Infinera

Sr. ASIC Design Engineer

Apr 2012 – Apr 2013 · 1 yr · Bengaluru Area, India

  • Understanding OIF-SAR (Segmentation and Reassembly) standard. Micro Architecture design of OIF-SAR IP and RTL development.
Micro Architecture designRTL developmentOIF-SAR standardASIC

Tejas networks

3 roles

Lead R & D Engineer

Promoted

Jul 2011 – Apr 2012 · 9 mos

  • Design, development, FPGA Implementation and target testing of --
  • 1. HDLC Over PCI-Express IP for In-Band Communications between network elements in SONET/SDH networks
  • 2. Circuit Emulation IP for transporting E1 signal over Packet Switched Networks
FPGA ImplementationHDLC Over PCI-ExpressCircuit Emulation IPFPGATelecommunications

Sr. R&D Engineer

Apr 2008 – Jun 2011 · 3 yrs 2 mos

  • Design, development, FPGA Implementation and target testing of --
  • 1. M13 MUX for multiplexing/de-multiplexing DS1 into DS3
  • 2. Ethernet Over PDH IP for transport of Ethernet packet over PDH networks
  • 3. Ethernet Over HDLC IP for In-Band Communications between Network Elements in SONET/SDH networks
  • and
  • FPGA Implementation of Ethernet MAC, Buffer Manager (Design also), GFP-F Framer and VCAT for transport of 10/100/1000 Mbps Ethernet signal over SONET/SDH networks
FPGA ImplementationEthernet Over PDHEthernet Over HDLCFPGATelecommunications

R & D Engineer

Jul 2006 – Mar 2008 · 1 yr 8 mos

  • Design, development, FPGA Implementation and target testing of 1) E1/T1/E3/DS3 signal mapping into SONET/SDH frame and 2) E1/T1 Framer for MSPP products
FPGA ImplementationE1/T1/E3/DS3 signal mappingFPGATelecommunications

Government college of engineering and leather technology

Lecturer

Jan 2002 – Dec 2003 · 1 yr 11 mos · Kolkata Area, India

  • Taught Basic Electronics, Analog and Digital Circuits, Communication Principles and Systems etc..

Signotron india private ltd

Engineer

Aug 2001 – Dec 2001 · 4 mos · Kolkata Area, India

  • Testing and debugging of Micro-controller based AC motor drives

Education

Indian Institute of Technology, Kharagpur

MS — Telecommunication Engineering

Jan 2004 – Jan 2006

Kalyani Government Engineering College

B.Tech — Electronics & Communication Engineering

Jan 1997 – Jan 2001

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