Ashish Goel — Director of Engineering

Experience in Semiconductor industry -> Manage SOC RTL and Verification right from Concept to Engineering sample delivery -> Interacting and negotiating with Global teams and ensuring the quality and timely deliverable -> Worked in various domains (laptop, desktop, wireless, networking chips, Graphics, Automotive & Consumer & industrial) -> Lead IP RTL delivery team & Verification and handling multiple IP delivery to multiple SOC -> Well versed with the entire flow from concept to qualification -> Experience in various flavors of verification like ABV, Formal Verification and Coverage driven random verification, Low Power Verification, GLS -> Worked on Macro, Micro architecture, RTL design & Support Validation (pre & post silicon) -> Provide solution to organization verification challenges -> Identifying/Implementing the methodology changes to increase productivity Specialties: Languages: C, C++, VHDL, Verilog, System Verilog, Vera,Perl,TCL, Shell, Makefiles Other Tools: Perforce, Clearcase, Design Sync, Certitude, HAL, CDC Methodologies: Formal, Functional, Low power, Assertion Based verification, UVM, GLS Knowledge in standard like DDR , 802.11a, JTAG, DIGRF, PCI, AHB, AXI Flash & various other peripherals IPs

Stackforce AI infers this person is a Semiconductor Verification Expert with extensive experience in SOC design and verification methodologies.

Location: Noida, Uttar Pradesh, India

Experience: 25 yrs 10 mos