Sandipan Sharma

Software Engineer

Delhi, India6 yrs 7 mos experience

Most Likely To SwitchAI Enabled

Key Highlights

Expert in Very-Large-Scale Integration (VLSI) design.
Proven track record in hardware engineering at Google.
Strong experience in DFT and testability solutions.

Stackforce AI infers this person is a Semiconductor Engineering Specialist with expertise in DFT and VLSI design.

Contact

Skills

Core Skills

Very-large-scale Integration (vlsi)Hardware Engineering

Other Skills

ATPGArduinoAutomatic Test Pattern Generation (ATPG)CDCCustom algorithmsDFT RTL CheckerEDAEmbedded SystemsFormal VerificationFusion compilerIJTAGIjtagInternet of ThingsJavaLangChain

About

Always in pursuit of a perspective and ready to indulge myself in any possible domain.

Experience

Google

3 roles

Hardware Engineer 3

Promoted

Nov 2024 – Present · 1 yr 4 mos · On-site

Co-Owner of Fusion Compile based Scan chain stitching flow. Supporting backend DFT team with user base spanning to 100+.
Leading cross domain engagement with EDA partners for new industry solutions and patch fixes for any bugs.
Anchored interactions for some hi-tech industry solutions for IJTAG protocol with EDA counterparts.

Fusion compilerIJTAGEDAVery-Large-Scale Integration (VLSI)Hardware Engineering

Hardware Engineer 2

Jul 2021 – Oct 2024 · 3 yrs 3 mos · On-site

I owned the spyglass based DFT RTL Checker flow for Testability at the design end. Also supported a group of 100+ end users. Designed DRC solutions with custom algorithms that cater to the user's needs.
Owned custom DFT reset and clocking architectures in the design and was responsible for maintaining standard implementation across multiple partitions.
Owner of ICL generator flow for any 3PIP IJTAG instrument and seemless integration in hierarchical fashion.
Also developed wrapper flow for mixed signal IPs for seemless integration with existing ICL and PDL support.

Spyglass TestMax AdvisorDFT RTL CheckerCustom algorithmsVery-Large-Scale Integration (VLSI)Hardware Engineering