Nikhil Patel

Software Engineer

Ahmedabad, Gujarat, India6 yrs 7 mos experience

Highly Stable

Key Highlights

6+ years of experience in IP/SoC verification.
Expert in VIP development using System Verilog and UVM.
Proficient in test plan creation and debugging complex scenarios.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in Hardware Verification and UVM methodologies.

Contact

Skills

Core Skills

Hardware VerificationUniversal Verification Methodology (uvm)System On A Chip (soc)

Other Skills

8051 MicrocontrollerAMBAAMBA AHBASIC verificationAXIAnalytical SkillsArchitectureAssertion Based VerificationC (Programming Language)C++CommunicationComputer SimulationsCpu BootCritical ThinkingDV

About

6+ yrs, Experienced IP/SoC verification engineer skilled in VIP development using System Verilog and UVM. Proficient in test plan creation, testbench automation, and debugging complex scenarios using a diverse toolset including C++ and Python.

Experience

Eteros technologies

Senior engineer-ASIC Verification

Oct 2024 – Present · 1 yr 5 mos · Ahmedabad, Gujarat, India · Hybrid

Einfochips (an arrow company)

2 roles

Senior Design Verification Engineer

Apr 2023 – Oct 2024 · 1 yr 6 mos

Design Verification Engineer

Jul 2019 – Mar 2023 · 3 yrs 8 mos

1. Worked on verifying Ethernet (40G, 100G) VIP development for all layers of ethernet on UVM platform
(Team project), my contribution includes.
> Update existing MAC VIP (10G) which can compatible for 40G and 100G.
> End to End score board development.
> Created tests for 100G (FEC and without FEC), includes error test cases
2. Our team is also responsible for creating PRBS VIP development, my contribution includes,
> Implemented driver and driver callback for run time error generation.
> Error test cases creation
3. Currently working on machine learning accelerating chip (SOC) verification, my role includes.
> Focused on Varification of one subsystem of SOC which is debug trace on C++ enc.
> Test cases development and sequence updates.
> Regression and coverage analysis, debugging failures.
> Validation activities, libs and tests development for validation tool
. . .

Ethernet VIP developmentUVMC++Test case developmentRegression analysisDebugging+2

Eitra - einfochips training & research academy ltd

Trainee

Jan 2019 – Jul 2019 · 6 mos · Ahmedabad, Gujarat, India

Taken brief training which includes
> Verilog, System Verilog and UVM.
> Shell and perl scripting.
> Developed test benches using SV and UVM.\
Also responsible for verifying Floating Point ALU, AHB lite protocols by creating SV, UVM TB (Team Project).