Hardik Sakhareliya

Software Engineer

Bangalore Urban, Karnataka, India6 yrs experience
Highly Stable

Key Highlights

  • Self-motivated professional in ASIC verification.
  • Proficient in SystemVerilog and UVM methodologies.
  • Experience across multiple engineering roles in semiconductor industry.
Stackforce AI infers this person is a semiconductor verification engineer with expertise in ASIC design and functional verification.

Contact

hardiksakhareliya.er@gmail.comLinkedIn

Skills

Other Skills

C (Programming Language)C++DVDebuggingLinuxMicrosoft OfficePerlSystem on a Chip (SoC)SystemVerilogUniversal Verification Methodology (UVM)Verilog

About

Self motivated professional with functional verification experience in ASIC using system verilog, UVM and c++.

Experience

Samsung semiconductor

Associate Staff Engineer

Jan 2025 – Present · 1 yr 2 mos · Bangalore, India

Einfochips (an arrow company)

2 roles

Senior Design Verification Engineer (Level 1)

Promoted

Jul 2024 – Jan 2025 · 6 mos · Ahmedabad, Gujarat, India

ASIC design verification engineer

Feb 2021 – Jul 2024 · 3 yrs 5 mos · Ahmedabad, Gujarat, India

Eitra - einfochips training & research academy ltd

asic verification trainee

Feb 2020 – Jan 2021 · 11 mos · Ahmedabad, Gujarat, India

Mascot electrotek pvt. ltd.

Instrumentation and Control Engineer

Dec 2018 – Feb 2020 · 1 yr 2 mos · Rajkot, Gujarat, India

Idmc limited

Training

May 2016 – May 2016 · 0 mo · Anand, Gujarat, India

Education

Jobs for Rajkot

Bachelor's degree

Jan 2013 – Jan 2017

Stackforce found 100+ more professionals with C (Programming Language) & C++

Explore similar profiles based on matching skills and experience

AD

Arnab Dan

Associate Software Engineer

at Bosch Global Software Technologies

Bengaluru, India4 yrs 5 mos exp
ECU AutomationEOL Testing
VIVEK KUMAR

VIVEK KUMAR

Hardware Engineering Manager

at NVIDIA

Bengaluru, India12 yrs 9 mos exp
Clock and Reset architecture verificationSoC verificationVerification methodology development
Nikhil Patel

Nikhil Patel

Senior engineer-ASIC Verification

at Eteros Technologies

Ahmedabad, India6 yrs 7 mos exp
Hardware VerificationSystem on a Chip (SoC)Universal Verification Methodology (UVM)
KS

Kirti Singh

Ad Traffic Associate

at Digital Remedy

Bangalore Urban, India3 yrs 7 mos exp
Ad TraffickingAdvertisingDigital MarketingMarketing Campaign ManagementProgrammatic Advertising
Ankit Garg

Ankit Garg

Senior ASIC Design Engineer

at Amazon

Bengaluru, India11 yrs 5 mos exp
Chip leadLeadershipRTL designVerification and Validation (V&V)
Hrishikesh C.

Hrishikesh C.

Coherency Verification Engineer

at Microsoft

Raleigh, United States7 yrs 3 mos exp
Design Verification TestingFunctional VerificationVerification and Validation (V&V)
Pavan Kumar Gunnamsetti

Pavan Kumar Gunnamsetti

GPU Verification Engineer

at Imagination Technologies

Hyderabad, India11 mos exp
Universal Verification Methodology (UVM)SystemVerilogVerilogDigital Electronics
T Manikantha

T Manikantha

Manager

at SBI Card

Gurugram, India9 yrs 9 mos exp