Ravi kumar Asadi — CEO
Lead Application Engineer at Cadence Design Systems with over 13 years of specialized experience in SoC, subsystem, and FPGA design and verification. Proficient in PARTL, PaGLS, Lpddr5, Verilog PLI, and advanced verification methodologies like SystemVerilog and UVM. Skilled in ASIC/FPGA verification, gate level simulation, and verification for protocols like PCIe, Ethernet, and ARINC 429. Contributed to diverse projects including LPDDR5 verification, GPU gate-level simulation, and 5G PHY network prototyping. Leveraged expertise in Matlab scripting, Simulink, and Xilinx DSP System Generator for FPGA-based prototyping in image and signal processing. Dedicated to delivering high-quality verification solutions and advancing the field of VLSI design.
Stackforce AI infers this person is a VLSI design expert with a focus on ASIC and FPGA verification.
Location: Bangalore Urban, Karnataka, India
Experience: 15 yrs 5 mos
Skills
- System On A Chip (soc)
- Uvm
- Asic/fpga Verification
- Fpga Verification
Career Highlights
- Over 13 years of experience in SoC and FPGA design.
- Expertise in advanced verification methodologies like UVM.
- Proficient in ASIC/FPGA verification and gate-level simulation.
Work Experience
Cadence
Lead Application Engineer (5 mos)
SiSoC Semiconductor Technologies Pvt Ltd.
Design Verification Engineer (3 yrs 4 mos)
Hitachi Energy
Research And Development Engineer (4 yrs 1 mo)
HCLTech
Lead Engineer (6 yrs 3 mos)
NXG Semiconductor Technologies
intern Engineer (1 yr 3 mos)
StellarIP Solutions
Trainee (0 mo)
Education
M.Tech at Sri Venkateswra College of Engineering and Technology Chittoor
Bachelor of Technology (B.Tech.) at Madanapally Institute of Technology and Science,JNTU University
Diploma at GMR Polytechnic Madanapalle
