Oct 2022 – Present · 3 yrs 5 mos · Santa Clara, California, United States

Nov 2018 – Mar 2021 · 2 yrs 4 mos · Gurgaon, Haryana, India

Sep 2017 – Oct 2018 · 1 yr 1 mo · Bangalore

Jan 2017 – Jun 2017 · 5 mos · Bangalore

• Project 1: Improvement of timing response in multi-threaded software UART communication of peripherals through FPGA.
• Worked on driver codes (C language-based) and improved the timing response of Electro-Optical (EO) camera, IR camera, Compass, GPS, Laser Range Finder communication response timings from FPGA-based Tonbo's thermal imaging video engine.
• Implemented python code for UART-based communication protocols from external devices to the FPGA-based Tonbo's thermal imaging engine.
• Project 2 : Implementation of a 3x3 Gaussian filter for the incoming analog video in the FPGA.
• Designed the pipelined State Machine-based architecture for filtering the incoming video stream by 3x3 kernel on FPGA.
• Implemented the above architecture on VHDL for handling high throughput of input pixels.
• Can be modified easily to support larger kernels, while giving output in accordance to company's video format

Aug 2016 – Dec 2016 · 4 mos · Goa, India

• Assisted the course instructors in the evaluation of hardware labs, software labs and projects assigned to the students.
• Took an official lecture under the Instructor-in-Charge on Verilog-Programming.

May 2015 – Jul 2015 · 2 mos · Pithapuram, Andhra Pradesh, India

• Objective: To reduce the breakdown time in the circular looms used by the NCIL.
• Outcome: 12% reduction in breakdown time which resulted in 5% increase in production.
• 1. Worked in a team of 3 interns.
• 2. Conducted time-and-motion study on the manufacturing process.
• 3. Improved routine maintenance procedure of the machines known as CLTI (Cleaning, Lubrication, Tightening and Inspection).
• 4. Suggested a performance-based incentive scheme for the workers.