Vaibhav Agrawal

Software Engineer

Noida, Uttar Pradesh, India11 yrs 5 mos experience

Key Highlights

Led design teams for high-performance SoCs.
Expert in low-power design for Snapdragon architectures.
Strong background in DDRPHY and CPUSS design.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in SoC and low-power design.

Contact

Skills

Core Skills

Soc DesignCpuss Design

Other Skills

Boot and securityLow-power DesignUPFDDRPHY DesignRTL DesignVerilogSynopsys toolsFormal VerificationElectronicsMatlabFPGAProgrammingVLSICDigital Electronics

About

FE design engineer with past experiences in DDRPHY, CPUSS and SoC design. Currently leading DDRSS FE Design Team for Snapdragon based SoCs. Lead the FE design team for SoC development of High performance General Purpose STM32. More than 5 years of experience in CPUSS design and development for Snapdragon SoCs. Skilled in FE Tools like Lint, CDC, CLP, VCS. Strong academic background in engineering professional with a Bachelor of Technology (B.Tech.) focused in Electronics and communications Engineering from M.N.N.I.T. Allahabad(U.P.).

Experience

Qualcomm

Staff Engineer

Apr 2025 – Present · 11 mos · Noida, Uttar Pradesh, India · On-site

Leading DDRSS Design team.

Stmicroelectronics

SoC FE Lead

Feb 2023 – Apr 2025 · 2 yrs 2 mos · Greater Noida

SoC FE Design lead for high performance STM32 with latest cortex processor.
Developed spec for STM32 along with the product architecture team.
Boot and Security module ownership.
Defined specs and developed flows for RTL generation and their checkers with CAD team.

Boot and securitySoC Design

Qualcomm

4 roles

Senior Lead Engineer

Dec 2020 – Jan 2023 · 2 yrs 1 mo

Lead Low power CPUSS Designs for Snapdragon SoCs.
Developed UPF for complete CPUSS designs with multiple power domains and crossings.
Development for clock controller and sequence based power controller for CPUSS.
Defined programming sequences to be shared with SW team for validation.

Low-power DesignCPUSS Design