Aman Gupta

CTO

West Godavari, Andhra Pradesh, India15 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in SOC Design and Ethernet integration.
Proficient in System Verification and C++ programming.
Strong background in Failure Mode and Effects Analysis.

Stackforce AI infers this person is a specialist in Computer Hardware with expertise in SOC design and verification.

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Skills

Core Skills

Soc DesignEthernetSystem VerificationC++

Other Skills

IntegrationIP SynthesisISO26262 complianceFailure Mode and Effects Analysis (FMEA)System Level verificationFPGA ValidationSilicon BringupTestplan creationLinuxVerilogFPGAProgrammingMatlabTSNMACSec

About

Experienced Application Specific Integrated Circuit Design Engineer with a demonstrated history of working in the computer hardware industry. Skilled in Matlab, System Verification, C++, Functional Verification, and Verilog. Strong engineering professional with a Masters's degree focused in Electronics and Communications Engineering from International Institute of Information Technology.

Experience

15 yrs

Total Experience

7 yrs 6 mos

Average Tenure

14 yrs 6 mos

Current Experience

Nvidia

5 roles

Chip Management

Promoted

Jul 2021 – Present · 4 yrs 9 mos

IP Manager

Apr 2019 – Jun 2021 · 2 yrs 2 mos

IP Lead

Jan 2018 – Mar 2019 · 1 yr 2 mos

Sr ASIC Design Engineer

Nov 2015 – Jan 2018 · 2 yrs 2 mos

Responsible for SOC Design and Integration of Ethernet IP in Tegra SOC. Responsibilities include defining requirements from Clocks, Memory Client, IO pads, Interrupts, Buses, and hooking up Ethernet IP in Tegra sub system along with taking the design through IP Synthesis, NA, DQ, Formal, Spyglass processes.
Also working on ISO26262 compliance of the Ethernet IP and Failure modes and effects analysis (FMEA).
Ownership for PWM and Tach design in Tegra.

EthernetSOC DesignIntegrationIP SynthesisISO26262 complianceFailure Mode and Effects Analysis (FMEA)

SOC Verification Engineer

Aug 2011 – Nov 2015 · 4 yrs 3 mos

Responsibilities included System Level (SOC) verification of Tegra IO IP's. Was responsible for
(a) creating SOC testplans,
(b) writing System level tests (C++),
(c) creating FPGA Validation testplans and executing on FPGA
(d) creating Silicon Bringup testplan and executing on Silicon
(e) SW and customer Support
Owned below IP's for SOC Verifcation during this time:-
1) SDMMC (SD3.0, eMMC5.0, SDIO) interfaces
2) Ethernet 1G MAC interface
3) PWM
4) Tach