Pratik Soni

Software Engineer

Bengaluru, Karnataka, India11 yrs 5 mos experience

Key Highlights

  • Over 7 years of experience in STA timing analysis.
  • Expertise in managing timing closure for PCIe Gen6 and CIO80.
  • Proven track record in mentoring and developing new engineers.
Stackforce AI infers this person is a Semiconductor and Telecommunications expert with a focus on digital design engineering.

Contact

Skills

Core Skills

Static Timing AnalysisTiming ClosureLogic Synthesis

Other Skills

AutomationProblem SolvingDigital IC DesignLECTeam LeadershipDMSAClock Tree SynthesisPTECOLeadership DevelopmentLeadershipCross-functional Team Leadershipc tsVerilogModelSimMatlab

About

Seasoned Digital Design Engineer with over 7 years of hands-on experience in STA timing analysis and advanced timing fixes using tools such as Tweaker and Primetime. My extensive background includes managing timing closure for complex IPs like PCIe Gen6 and CIO80, as well as high-performance digital blocks with frequencies up to 2GHz across multiple technology nodes from 18A to 14nm. I have a proven track record in overseeing chip-level STA signoff, particularly for designs involving critical memory interfaces. My role often involves tackling complex timing issues across various voltage ranges and technology nodes, requiring precise validation and optimization to achieve design goals. My hands-on approach to timing analysis has enabled me to deliver high-quality results for large-scale designs and intricate IPs, consistently meeting demanding performance and reliability standards. Throughout my career, I have been actively involved in validating STA methodologies and collaborating with Place and Route (PnR) engineers. This collaboration ensures timely and effective feedback, which significantly contributes to achieving faster convergence in design processes. My ability to provide actionable insights and maintain open lines of communication with various stakeholders has been crucial in streamlining workflows and enhancing overall design efficiency. My hands-on experience also includes continuous improvement, particularly in optimizing design flows and reducing ECO cycle runtimes. I have applied my expertise in timing optimization to resolve timing issues across 18A, 3nm, 6nm, 7nm, and 8nm technologies, effectively managing ECO deliverables and ensuring timely project completion. Throughout my career, I have been dedicated to mentoring and developing new engineers and sharing my knowledge and experience to foster a collaborative and high-performing team environment. My commitment to enhancing the PPA (Power, Performance, Area) matrix of designs and my ability to manage multiple projects simultaneously reflect my adeptness in driving innovation and achieving excellence in digital design engineering. Please feel free to reach out to me at sonipratik07@gmail.com.

Experience

11 yrs 5 mos
Total Experience
3 yrs 3 mos
Average Tenure
1 yr 6 mos
Current Experience

Mediatek

4 roles

Staff Engineer

Promoted

Oct 2024Present · 1 yr 6 mos · Bengaluru, Karnataka, India · On-site

Staff Engineer

Jun 2021Jan 2022 · 7 mos

  • Executed STA timing analysis and complex timing clean-up, ensuring successful timing closure for the Modem design.
  • Enhanced design flow processes to reduce ECO cycle runtime and ensure timely delivery of ECOs.
Digital IC DesignAutomationStatic Timing AnalysisTiming Closure

Senior Engineer

Promoted

Sep 2018May 2021 · 2 yrs 8 mos

  • Oversaw sub-system and block-level timing closure for complex Modem designs, implementing flow improvements to reduce ECO cycle runtime.
  • Managed timely delivery of ECOs, tracked progress, and compiled data from multiple stakeholders to ensure accurate and on-schedule outcomes.
  • Utilized expertise in timing optimization to generate ECOs for resolving timing issues across 6nm, 7nm, and 8nm technologies and performed synthesis for sub-systems using Design Compiler.
Problem SolvingAutomationStatic Timing AnalysisTiming Closure

Engineer

Jul 2017Sep 2018 · 1 yr 2 mos

  • Performed synthesis for sub-systems using Design Compiler and Genus and reviewed the clock tree structure post-CTS to ensure optimal performance.
  • Managed block-level timing closure with a focus on setup, hold, and timing DRCs and conducted quality checks prior to Place and Route (PnR).
Logic SynthesisLEC

Intel corporation

Digital Design Engineer

Jan 2022Aug 2024 · 2 yrs 7 mos · Bangalore Urban, Karnataka, India · On-site

  • Managed STA signoff for complex IPs, including PCIe Gen6, CIO80, and DTS, ensuring precise timing closure and compliance.
  • Validated STA methodologies for HSIO-IPs, contributing to accurate and effective timing analysis.
  • Collaborated closely with Place and Route (PnR) engineers, providing timely and actionable feedback to enhance design convergence and efficiency.
AutomationProblem SolvingStatic Timing AnalysisTiming Closure

Indian inst of technology hyderabad

Research Associate

Aug 2014Jul 2017 · 2 yrs 11 mos · Hyderabad Area, India

Education

Indian Institute of Technology Hyderabad

Master of Technology (M.Tech.) — VLSI and Microelectronics

Jan 2014Jan 2017

Shree guru gobind singhji institute of engineering and technology

Bachelor of Technology (BTech) — Electronics and telecommunication

Jan 2010Jan 2014

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