Pratik Soni — Software Engineer
Seasoned Digital Design Engineer with over 7 years of hands-on experience in STA timing analysis and advanced timing fixes using tools such as Tweaker and Primetime. My extensive background includes managing timing closure for complex IPs like PCIe Gen6 and CIO80, as well as high-performance digital blocks with frequencies up to 2GHz across multiple technology nodes from 18A to 14nm. I have a proven track record in overseeing chip-level STA signoff, particularly for designs involving critical memory interfaces. My role often involves tackling complex timing issues across various voltage ranges and technology nodes, requiring precise validation and optimization to achieve design goals. My hands-on approach to timing analysis has enabled me to deliver high-quality results for large-scale designs and intricate IPs, consistently meeting demanding performance and reliability standards. Throughout my career, I have been actively involved in validating STA methodologies and collaborating with Place and Route (PnR) engineers. This collaboration ensures timely and effective feedback, which significantly contributes to achieving faster convergence in design processes. My ability to provide actionable insights and maintain open lines of communication with various stakeholders has been crucial in streamlining workflows and enhancing overall design efficiency. My hands-on experience also includes continuous improvement, particularly in optimizing design flows and reducing ECO cycle runtimes. I have applied my expertise in timing optimization to resolve timing issues across 18A, 3nm, 6nm, 7nm, and 8nm technologies, effectively managing ECO deliverables and ensuring timely project completion. Throughout my career, I have been dedicated to mentoring and developing new engineers and sharing my knowledge and experience to foster a collaborative and high-performing team environment. My commitment to enhancing the PPA (Power, Performance, Area) matrix of designs and my ability to manage multiple projects simultaneously reflect my adeptness in driving innovation and achieving excellence in digital design engineering. Please feel free to reach out to me at sonipratik07@gmail.com.
Stackforce AI infers this person is a Semiconductor and Telecommunications expert with a focus on digital design engineering.
Location: Bengaluru, Karnataka, India
Experience: 11 yrs 5 mos
Skills
- Static Timing Analysis
- Timing Closure
- Logic Synthesis
Career Highlights
- Over 7 years of experience in STA timing analysis.
- Expertise in managing timing closure for PCIe Gen6 and CIO80.
- Proven track record in mentoring and developing new engineers.
Work Experience
MediaTek
Staff Engineer (1 yr 6 mos)
Staff Engineer (7 mos)
Senior Engineer (2 yrs 8 mos)
Engineer (1 yr 2 mos)
Intel Corporation
Digital Design Engineer (2 yrs 7 mos)
Indian Inst of Technology Hyderabad
Research Associate (2 yrs 11 mos)
Education
Master of Technology (M.Tech.) at Indian Institute of Technology Hyderabad
Bachelor of Technology (BTech) at Shree guru gobind singhji institute of engineering and technology