Maruthi Maddala

Software Engineer

Bengaluru, Karnataka, India0 mo experience

Key Highlights

  • Expert in UVM and SystemVerilog for ASIC design.
  • Proficient in Python and TCL scripting for verification.
  • Hands-on experience in layout design using Cadence tools.
Stackforce AI infers this person is a Semiconductor Verification Engineer with strong skills in ASIC design and verification methodologies.

Contact

LinkedIn

Skills

Core Skills

Universal Verification Methodology (uvm)Systemverilog

Other Skills

APBAdobe PhotoshopCC++Cadence VirtuosoData StructuresDigital ElectronicsFunctional VerificationModelSimOpenCVPythonQuestaSimTCLUVMVHDL

Experience

Cisco

ASIC Engineer

Oct 2018 – Present · 7 yrs 5 mos · Bangalore

  • Designed UVM based Verification environments for multiple modules from scratch.
  • Worked on DMA blocks , Offload (Compression , Encryption , Fingerprint ) blocks , Real time Analytics block.
  • Writing test benches to verify design features and meet coverage goals in UVM & SV.
  • Scripting with python whenever needed.
  • Scripting with TCL for testing during chip bring-up
C++SystemVerilogUniversal Verification Methodology (UVM)PythonTCL

Silab tech pvt ltd

2 roles

Summer Trainee

May 2017 – Jul 2017 · 2 mos · Bengaluru Area, India

  • Created a verification environment for a switch network & an AMBA-APB slave using SV
  • Used Questa Sim for Simulation
SystemVerilogQuestaSim

Summer Trainee

Jun 2016 – Jul 2016 · 1 mo · Bengaluru Area, India

  • Layout Designing Using CADENCE Virtuosos Tool
  • Designed standard cells (AND,OR,NOT,XOR) with various drive strengths
  • Designed an Op-Amp block in the tsmc 60 nm foundry.
  • Cleared DRC and LVS for all the designs
Cadence Virtuoso

Education

National Institute of Technology, Kurukshetra, Haryana

Bachelor of Technology - BTech

Jul 2014 – Jun 2018

Sri Chaitanya jr College

12th — MPC

Jan 2012 – Jan 2014

St. Aloysius AI High School

10th

Jan 2011 – Jan 2012

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