Vishal Thakral

Product Engineer

India6 yrs 3 mos experience

Key Highlights

5+ years of experience in IP and subsystem level verification.
Expertise in SystemVerilog and UVM based verification.
Proven track record in automating verification processes.

Stackforce AI infers this person is a Semiconductor Verification Engineer with strong automation and EDA tool validation skills.

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Skills

Core Skills

Functional VerificationSystemverilogEda Tools ValidationAutomation

Other Skills

AXI BFMAnalytical SkillsBashC (Programming Language)C++Coverage ClosureDMADigital ElectronicsGCOVLinuxMongoDBPCIePerlPerl AutomationPython

About

- Senior Verification Engineer with 5+ years of experience with IP as well as subsystem level verification. - I have exposure to System verilog/UVM based verification TB. Also, worked on System verilog assertions and coverage. - I have done the verification of DMA IPs for full product cycle ranging from understanding spec, and creating verification plan to the Regression and Coverage closure. - I have worked on integrating AXI BFM and PCIe Phy in the verification environment. - I have good scripting skills and have automated a number of day to day activities using Perl/Python/Csh/Bash scripting. Skills - VLSI Skills - Verilog, VHDL, SystemVerilog, UVM, Perl, Bash/Csh, Python, DMA Protocols - AXI streaming, AXI memory mapped, APB, AVST, AVMM, PCIe(Transaction layer) CAD Tools - Xcelium, VCS, Verdi, JasperGold, Genus, Modus, Xilinx ISE, QuestaSim.

Experience

Microsoft

Design Verification Engineer

Oct 2024 – Present · 1 yr 5 mos

Intel corporation

2 roles

Senior Verification Engineer

Jan 2024 – Oct 2024 · 9 mos

Verification Engineer

Nov 2021 – Jan 2024 · 2 yrs 2 mos

Responsible for verifying PCIe based DMA IP at block and system level.
Created testplan, coverage plan for various features followed by reviewing it with stakeholders and planned the execution.
Integrated AXI BFM agents, sequences in existing TB, created layering agents for protocol conversion.
Created UVM infrastructure for Tile bring-up at system level and inject multi-segment and multi-packet scenarios.
Enhanced structural flexibility in TB to enable Port-bifurcation verification. Debugged and Concluded complex scenarios at system level.
Part of taskforce to complete customer ask for providing features two cycles early, colleborated with RTL Designers & Architects and Filed 21 critical bugs within 3 weeks to ensure IP quality
Leveraged my scripts skills to automate and improve the regressions, failure bucketization and debugging experience.

PCIeDMAUVMAXI BFMVerification PlanRegression+4

Cadence design systems

VLSI Engineer 1

Jun 2020 – Nov 2021 · 1 yr 5 mos

Worked on validation of various features of Xcelium simulator.
Developed a perl based system verilog randomization code generator which targetted the constraint solver validation.
Developed an autonomous system to select a suite of testcases for nightly build having max possible coverage and min possible runtime thereby reduced test count from 3M to 0.05M i.e 97% reduction in test count and 38% reduction in execution time using Python, MongoDB, GCOV skills
Created an autonomous test execution system which simulated all testcases which exposed bugs after every release & also gives the CL for passing ones that fixed it.
Implemented a tool flow to validate EDA tools involved in RTL to GDS flow namely Xcelium, Genus, Modus, Eq checker.

XceliumPerlPythonMongoDBGCOVEDA Tools Validation+1

Mentor graphics

System design & verification Internship

May 2019 – Jul 2019 · 2 mos · Noida Area, India

Had experience with Verilog HDL, System Verilog HDL, System Verilog assertions & coverage driven test benches and Quick introduction to UVM.
Developed a layered coverage driven test bench for LC3 microprocessor verification.
Best performer in the internship among the 30 participants from top tier colleges across India.
Earned Certificate of Appreciation.

VerilogSystem VerilogUVM

Iit bombay heritage foundation

E-yantra Robotics(IIT Bombay)

Aug 2017 – Feb 2018 · 6 mos · bombay

Worked on a project that involves implementation of Transporter Bot for transporting various fruits segregated in different baskets respectively through the shortest path. The real-time simulation of the bot was also shown in Blender game engine.
HW used - ATMEGA2560, Zigbee, Arduino Nano, Motors
SW/Languages used - Blender, Arduino IDE, System C