Mar 2019 – Jan 2020 · 10 mos · Penang, Malaysia

• (1) Worked on Intel’s PCIe subsystem project and doing PCIe multi-link controller and PIPE direct mode verification. This involves verification from scratch in UVM, understanding complete high level architecture along with giving training to the team (for sub-system connectivity as well as
• PCIe PIPE 5.1 specification) and running all SVT PCIe TS tests on the subsystem level and debugging them for closure to 100% pass coverage.
• (2) Worked on multi-channel Ethernet IP Auto-Negotiation and its related resets feature verification. The goal was to port all the tests/sequences (already running on single channel IP) and make them working on multi-channel IP environment by creating new macros to run same/different sequences on different channels.

Jun 2015 – Jan 2019 · 3 yrs 7 mos · New Delhi Area, India

• Worked on the PCI Express GEN1/GEN2/GEN3/GEN4/GEN5 Verification IP using SystemVerilog (UVM):
• (1) Done implementation and verification of PHY specific power states, L1SS PIPE sideband signals, user controlled RX equalization, dynamic equalization (dynamic preset coefficient updates) and PIPE 4.4/5.1 Low Pin Count updates in VIP.
• (2) Developed and verified 10-bit field scaling GEN4 feature in passive monitor in UVM.
• (3) Done FLR implementation for passive monitor in UVM.
• (4) Added completion timeout disable mechanism in passive monitor in UVM.
• (5) Worked on development of physical layer checks implementation in monitor in UVM.
• (6) Added new features and fixed issues in VIP.
• (7) Done reviews and provided feedback on coverage and specification linking features that were developed by other teams for monitor.
• (8) Adding different Articles/FAQs for resolving queries from customers.
• (9) Conducting interviews to assess PCI Express protocol knowledge.

Sep 2011 – May 2015 · 3 yrs 8 mos · New Delhi Area, India

• Worked on the PCI Express GEN1/GEN2/GEN3 Verification IP using SystemVerilog (OVM/UVM) and Verilog:
• (1) Worked on development of data link layer and transaction layer monitor from scratch in UVM with addition of basic and compliance checks. Got Team Excellence award and STAR award for this implementation.
• (2) Added topology, configuration space and system architecture checks for passive monitor in UVM.
• (3) Implemented configurable expected response (CER) for TLPs in passive monitor in UVM.
• (4) Got Perfect Survey award a lot of times for the timely support to the customers. Also found a lot of bugs in DUT.
• (5) Created multiple environments in Verilog and OVM with different numbers of BFM and bus-monitors instantiated in it.
• (6) Added support and new cases related to Expansion-ROM in VIP.
• (7) Added equalization feature, created test plan and test cases related to equalization in VIP.
• (8) Implemented different LTSSM and low power states on PIPE interface in VIP. Got SPARK award for this accomplishment.
• (9) Implemented L1 sub-states ECN in VIP. Got Team Excellence award for this accomplishment.
• (10) Added new features and fixed issues in VIP.
• (11) Added different Articles/FAQs for resolving queries from customers. Got Perfect Survey award a lot of times for the support from the customers.
• (12) Handled the release, regression and validation process for VIP.

Apr 2011 – Aug 2011 · 4 mos · New Delhi Area, India

• Worked on the PCI Express GEN3 verification IP using Verilog:
• (1) Basically worked on Transaction Layer. Added new cases to get 100% coverage.
• (2) Handled the release, regression and validation process for VIP.

Oct 2010 – Mar 2011 · 5 mos · Gurgaon, India

• Worked on ECM (Enterprise Content Management) domain and performed manual and automated testing. Performed Manual Testing of web based and client server application along with working on Test and Defect Management tools like Testlink- Bugzilla and Quality Centre and Automation testing tools like QTP 9.2, Load Runner 8.0 and JMeter. Was also involved in writing test cases, Integration Testing and System Testing. Tool used are Documentum and Intervowen.