Aug 2019 – Sep 2021 · 2 yrs 1 mo · Greater Bengaluru Area

• Driving Formal Verification for Imaging and Camera Technology Group. Developed and deployed a new formal verification methodology. Leveraging FV for successfully verifying AI/ML based designs, used in image processing.

Oct 2015 – Aug 2019 · 3 yrs 10 mos · Greater Hyderabad Area

• Formal Verification of Instruction Fetch Unit for CPU.
• Formal Verification of Execution unit for CPU.
• Developing Verification IPs.
• FV tools customization/automation.
• Modelling interface units.
• Writing assertions and constraints for control path.
• Clock gating verification.
• Formal coverage analysis.

Jul 2015 – Oct 2015 · 3 mos · Greater Hyderabad Area

• Design & Verification of a high-performance CPU - VISC Architecture at unit level (Scheduler & Execution).
• TestBench Work: Writing UVM Agent (Driver/Monitor) using system Verilog.
• Writing Test plans and test cases.
• Writing Constraints, Coverage and Assertions (SVA) using System Verilog.
• Worked on complete verification of Floating Point Unit (FPU).

May 2012 – Jun 2015 · 3 yrs 1 mo · Greater Hyderabad Area

• Functional verification of a super scalar CPU(VISC).
• Worked on scheduler and execution unit mainly for ISA, data path control path verification.
• Complete verification of Floating point unit.
• Writing Assertion, Coverage, Tests, Testplans.

Feb 2012 – Apr 2012 · 2 mos · Greater Hyderabad Area

• Working on Design and Verification of Microprocessor using UVM and System Verilog