Ashutosh T.

Software Engineer

Bengaluru, Karnataka, India14 yrs 2 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Functional Verification and System on a Chip design.
  • Proven track record in performance validation and integration of CPU and GPU.
  • Strong background in low-power design and power management.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC and SoC design.

Contact

LinkedIn

Skills

Core Skills

Functional VerificationSystem On A Chip (soc)

Other Skills

ARM ArchitectureASICBase band controllerBoot and test flowBuild and simulationCC++CPU power statesCPU test generationData pathDebuggingDigital ElectronicsEDAGate level synthesisHardware

About

Currently working in Nvidia as Senior Verification/Validation Engineer

Experience

14 yrs 2 mos
Total Experience
14 yrs 2 mos
Average Tenure
14 yrs 2 mos
Current Experience

Nvidia

4 roles

Senior ASIC Engineer -I

Apr 2017 – Present · 9 yrs 2 mos

  • PCIE Generation 5.0
  • Performance validation of data path for system fabric : computing bandwidth and latency
  • Integration of CPU and GPU:
  • Build and simulation
  • Boot and test flow
  • Tool migration
  • System-C modelling for IP's
  • Gate level synthesis
  • Post silicon SOC Bring-up
PCIE Generation 5.0Performance validationData pathSystem fabricIntegration of CPU and GPUBuild and simulation+7

Senior ASIC Engineer

Promoted

Apr 2014 – Mar 2017 · 2 yrs 11 mos

  • Infra development for CPU test generation
  • Safety features in RTL
  • Unit & System level clocks functional verification
  • System Gate level synthesis
Infra developmentCPU test generationSafety features in RTLUnit & System level clocks functional verificationSystem Gate level synthesisFunctional Verification+1

ASIC Design Engineer

Jul 2012 – Mar 2014 · 1 yr 8 mos

  • Memory subsystem interaction between Controller and IO
  • Base band controller: PCIe bus verification
  • Functional Verification of low power aspects of Tegra
  • Power monitors and tools
  • CPU power states and interaction with SOC
  • Power saving IO features
Memory subsystem interactionBase band controllerPCIe bus verificationFunctional VerificationLow power aspects of TegraPower monitors and tools+3

Intern

Jan 2012 – Jun 2012 · 5 mos

  • Power management of Tegra
Power management of Tegra

Education

Indian Institute Of Information Technology Allahabad

Bachelor of Technology (B.Tech.)

Jan 2008 – Jan 2012

Rani Laxmi Bai Memorial School (R.L.B.)

senior secondary

Stackforce found 100+ more professionals with Functional Verification & System On A Chip (soc)

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