Kamna Varshney

Product Manager

Delhi, India19 yrs 11 mos experience

Highly Stable

Key Highlights

Expert in EDA tools and ASIC design.
Proven track record in product validation and feature management.
Strong programming skills in multiple languages.

Stackforce AI infers this person is a specialist in EDA and ASIC design with extensive validation experience.

Contact

Skills

Core Skills

EdaAsic

Other Skills

CC-shellFeature ValidationFunctional VerificationI2CModelSimOasys-FormalproOasys-RTLOpen Verification MethodologyPCIePerlPowerProRTL codingShell ScriptingShell script

About

- Working as head of Customer Support Team for Front-End Issues for PowerPro tool in Mentor Graphics (SiemensEDA) -Worked on SOC validation in Freescale Semiconductor -Worked as Product Validation Engineer in Mentor Graphics India Pvt Ltd. - Worked as ASIC Design Engineer having experience on PCI express, PCI, USB2.0, ISA, I2C, UARTs, Parallel Port etc. - Having exert hands on for multiple EDA tools: PowerPro, SlecPro, FormalPro, Oasys, Onespin, Precision, Xilinx FPGA, Altera FPGA Specialties: Having knowledge of Verilog, System Verilog, VHDL, C, Perl, Python, Tcl, Shell scripting

Experience

Cadence design systems

Senior Principal Product Validation Engineer

Aug 2022 – Present · 3 yrs 7 mos · Noida, Uttar Pradesh, India

Mentor graphics

4 roles

Engineering Manager

Promoted

Jan 2021 – Aug 2022 · 1 yr 7 mos

Member Consulting Staff

Aug 2017 – Jan 2021 · 3 yrs 5 mos

Worked on Feature Validation & Release Management of PowerPro.
Worked as Product Validation Engineer for ASIC synthesis tool named Oasys-RTL. Worked closely on Oasys-Formalpro Integration & validation on customer designs.

PowerProOasys-RTLOasys-FormalproEDAASIC

Lead Member Technical Staff

Aug 2010 – Aug 2017 · 7 yrs

Product Validation Engineer

Apr 2009 – May 2010 · 1 yr 1 mo

Working in Precision Product Validation group. Creation of automated test environment including test cases & status reporting mechanism for product validation.
Technology : Verilog, VHDL, System Verilog, Shell script, Perl.

VerilogVHDLSystem VerilogShell scriptPerlEDA

Freescale semiconductor (client of masamb electronics)

Senior Design Engineer

May 2010 – Aug 2010 · 3 mos

Moschip

ASIC Design Engg.

May 2006 – Apr 2009 · 2 yrs 11 mos

Worked on ASIC Design/Verification having experience on PCI, PCI express, ISA,I2C, UART, USB2.0, USB3.0 etc
PCIe Based Peripheral Controller : Worked on PCIe based Peripheral Controller through which communication ports will come out through PCI express lane.
PCIe Based Multiport USB Controller : Worked on PCIe based Multiport USB Controller through which USB ports will come out through PCI express lane.
Have experience in Verilog, System Verilog, VHDL, Perl, C-shell, NC-verilog etc.

VerilogSystem VerilogVHDLPerlC-shellASIC