Oct 2013 – Jul 2016 · 2 yrs 9 mos · Austin, Texas Metropolitan Area · On-site

• Project Management: Led a team of 7 engineers to deliver reliable verification of complex Digital Networking HW accelerators and Power PCs.
• Innovation: Innovated new hardware verification methodologies for Power CPU’s Memory management unit.

Jun 2013 – Sep 2013 · 3 mos · Greater Bengaluru Area · On-site

• Performance Validation: Validated Tegra chips in collaboration with the Architecture performance team to optimize chip performance.

Jan 2011 – May 2013 · 2 yrs 4 mos · Noida, Uttar Pradesh, India

• Design Verification: Contributed to verification of Freescale's next-generation Multi-threaded Multi-core processor; responsible for verification of MMU unit of Processor and BIST engines of Core and Platform memories
• Product Development:
• 1. Test bench Infrastructure development, Worked on MMU's standalone environment with external drivers, random stimulus, and C++ model-based checker
• 2. Developed BIST Verification IP and verified Core and platform-level BIST engines using the same
• 3. Responsible for functional coverage identification and coding, Verif plan development and test case development, debugging, and coverage completion

Jul 2008 – Dec 2010 · 2 yrs 5 mos · Greater Delhi Area · On-site

• Customer Support: Provided on-site support to integrate nSys Verification IP suite with working environment across US, Israel, India for Qualcomm, NVIDIA, Texas Instruments, Broadcom, Applied Materials, and AMD.
• Communication Skills: Presented new USB3 technology verification suite at Design Automation & Test conference.