Devesh Kumar

Software Engineer

Delhi, India14 yrs 9 mos experience
Highly Stable

Key Highlights

  • Expert in Functional Verification methodologies
  • Proven track record in IP and SOC verification
  • Strong background in SystemVerilog and VHDL
Stackforce AI infers this person is a seasoned expert in ASIC design and verification within the semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

Functional VerificationSystemverilogVmmVhdlOpen Verification Methodology

Other Skills

ASICCC++DDR Memory Controller IP VerificationDevelopment and Verification of VIPEDAIP level verificationSOC verificationVerilogsub system level verificationuvm

Experience

Cadence design systems

Principal Design Engineer

Nov 2022 – Present · 3 yrs 4 mos · Noida, Uttar Pradesh, India

  • DDR Memory Controller IP Verification
DDR Memory Controller IP VerificationFunctional VerificationSystemVerilog

Stmicroelectronics

Technical Lead

Mar 2020 – Nov 2022 · 2 yrs 8 mos · Noida, Uttar Pradesh, India

  • IP level, sub system level and SOC verification.
IP level verificationsub system level verificationSOC verificationFunctional VerificationVMM

Altran

Senior Engineer

May 2018 – Mar 2020 · 1 yr 10 mos · Noida, Uttar Pradesh, India

  • IP level and sub system level verification.
IP level verificationsub system level verificationFunctional VerificationVHDL

Synopsys

Senior Research And Development Engineer

Jul 2011 – May 2018 · 6 yrs 10 mos · Greater Delhi Area

  • Development and Verification of VIP.
Development and Verification of VIPFunctional VerificationOpen Verification Methodology

Education

Bharati Vidyapeeth

Bachelor of Technology (B.Tech.) — Electronics and Communications Engineering

Jan 2007 – Jan 2011

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