Vikrant Kapila

CTO

San Jose, California, United States14 yrs 3 mos experience
Highly StableAI Enabled

Key Highlights

  • Led global teams across multiple countries.
  • Expert in System Architecture and FPGA performance.
  • Proven track record in delivering high-revenue solutions.
Stackforce AI infers this person is a high-level architect in the semiconductor industry, specializing in FPGA and system architecture.

Contact

Skills

Core Skills

System ArchitectureFpgaPerformance ModelingPerformance EngineeringAiPerformance ArchitectureTeam LeadershipInterconnectHardware ArchitectureSystemcHw-sw Co-designDse

Other Skills

5GAXIAlgorithm DesignAlgorithm DevelopmentAlgorithmsCC++CommunicationComputer ArchitectureDDR controllerDRAM memory sub-systemData Center ArchitectureData StructuresDebuggingDesign Space Exploration

About

Vikrant Kapila, Principal Engineer, Chief Architect and Director at Intel, is recognized within Intel and the industry as top domain-expert and advisor in System Architecture, Power Performance modeling, Design Space Exploration (DSE) and optimizations. His extensive knowledge spans solution stack from DDR, HBM, NoC, PCIe, AI accelerators to system applications like AI, IPU (SmartNIC) and other networking applications. He has strong proven track record of driving architecture, design, and post silicon to deliver best-in-class multi-billion-dollar revenue Datacenter and Client Computing solutions. Vikrant Kapila has a history of effectively cultivating essential talent and cultivating comprehensive technical capabilities from their foundational stages. Having led architecture and performance teams in the United States, Canada, Singapore, Malaysia, and India, he is enthusiastic about propelling advancement, nurturing innovation, and building high-performing teams to achieve outstanding results. Vikrant Kapila possesses extensive experience working with tier-1 data center customers and holds substantial working relationships with prominent third-party tools and IP partners such as Synopsys and Arteris. His background includes hands-on involvement in IP selection, configuration, and optimization for multiple generations. His key strengths lie in defining and constructing intricate hardware and software systems, working alongside executives, clients, and ecosystem partners to deliver top-tier products. Vikrant excels in recognizing opportunities, crafting compelling visions, and overseeing all system facets to achieve exceptional outcomes.

Experience

Altera

Principal Engineer (Director) | Chief Architect Agilex 5

Aug 2023Present · 2 yrs 7 mos · San Jose, CA · Hybrid

  • Chief Architect Agilex 3 & Agilex 5 Products.
  • Lead Processor and Network-on-Chip (NoC) Architect for all future FPGA products.
  • Head of performance modeling, analysis, and optimization for FPGA device SoC family.
  • Leading global team of SoC and performance architects
System ArchitecturePower Performance modelingDesign Space ExplorationFPGA

Intel corporation

2 roles

Lead Performance Architect | Technical Team Leader

Aug 2020Aug 2023 · 3 yrs · On-site

  • Led Intel's Agilex FPGA SoC as Performance Architect, outperforming the competition.
  • Developed & led high performance team of 20+ architects across US, Singapore, Penang & India.
  • Developed FPGA's 1st succesful performance exploration solution and deployed it across 5+ products.
  • Took projects from architectural exploration/definition through design, post-silicon bring up& debug.
  • Led performance for products targeting emerging markets e.g AI, SmartNIC (IPU), 5G etc.
Performance EngineeringAISmartNIC5G

Sr. Staff System Architect

May 2018Aug 2020 · 2 yrs 3 mos · On-site

  • Owned Hardware Architecture specifications for Interconnect and DRAM memory sub-system.
  • Served as Chip Architect within Systems Engineering at Intel-CCG
  • Led SoC performance from architecture to silicon including creation of performance models for SoCs
  • Led collaborations with synopsys and Arteris for IP selection, configuration and optimization.
InterconnectDRAM memory sub-systemPerformance modelsPerformance Engineering

Synopsys inc

Senior R & D Engineer

Jun 2012May 2018 · 5 yrs 11 mos · Noida Area, India

  • Proficient in developing and utilizing SystemC TLM-based tools for architecture PnP analysis.
  • Led the technical team for Task Graph Generator technology, enabling HW-SW co-design and DSE.
  • Developed a SystemC cycle-accurate model for synopsys designware DRAM Memory Controller.
  • Demonstrated experience and expertise in defining the microarchitecture of DRAM Memory controller.
SystemCTLMHW-SW co-design

St microelectronics

Internship

Jan 2011Jun 2011 · 5 mos · Greater Noida

  • Developer of Ultramixer SystemC/TLM model. A DDR controller front end IP, aiming at reordering the DDR requests in order to maximize DDR use and satisfy latency requirements.
SystemCDDR controller

Education

Indian Institute of Technology, Delhi

Master of Science (M.S.) Research | 9.136 — Computer Engineering

Thapar Institute of Engineering & Technology

B.E — ECE

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