Jun 2023 – Present · 2 yrs 9 mos

• USB4 Transactor
• Architected USB4 Subsystem Transactor integrating seven RTL IPs and complex software layers.
• Created connection manager software using novel bare-metal driver methodology, reducing development time from 6 months to 1 month.
• Published a paper at Synopsys Engineering innovation leadership conference.
• Packaged and deployed complete solution (10 components, example, regressions) to a major customer.
• AMBA Transactor
• Led AMBA (AXI, CHI, APB) transactor deployments
• Collaborated with customers to define functional requirements for new features, performance optimization, and quality enhancement.

Jan 2021 – May 2023 · 2 yrs 4 mos

• ENET 1.6T Transactor
• Developed ENET MAC 800G and 1.6T Transactor from ground up.
• USB Monitor and Transactor
• Created completely new USB Monitor resolving multi-instance issues and SLED support
• Redesigned test bench architecture eliminating all synchronization issues.
• Enhanced product based on feedback from multiple customers for improved ease of use and faster deployment
• USB Device Virtual Solution
• Developed novel method integrating real USB devices with transactor, eliminating need for complex device-side testbenches.
• Published a paper at DVCON, USA, 2025 highlighting the significance of novelty.

Jun 2018 – Dec 2020 · 2 yrs 6 mos

• USB Transactor
• Created USB DPI Transactor from legacy USB ZCEI Transactor deployment, Supports USB 2.0 (UTMI), USB 3.0, USB 3.1 (PIPE4), and USB 3.2 architecture for Host and Device configurations.
• Developed HW wrapper with AXI SV-C DPI layer over USB DRD IP, and a SW wrapper over Linux xHCI/gadget driver.
• Achieved 3.5X gain in HS speed, and 12.5X gain in SS/SSP speed over legacy Transactor.
• Developed API interfacing for Proxy drivers that interacts with QEMU/Virtual box, enabling verification through existing Linux drivers.
• Deployed and supported the solution for multiple customers, including Fortune 500 companies.
• Mentored interns in getting the tasks complete.
• XLVIP – Accelerated Verification IP
• Key contributor to methodology enabling UVM tests to run in emulation domain, eliminating duplicate test suite development.
• Prototyped the methodology on UFS Host and Device from scratch.
• Achieved 101x performance improvement: simulation 15 hours → emulation 10 minutes

Jun 2015 – May 2018 · 2 yrs 11 mos

• UFS Transactor
• Enhanced UFS Transactor with comprehensive debug features including L1/L1.5 layer monitor and checker with 40+ protocol checks
• Prototyped split UFS capability, major advancement in waveform debugging
• Achieved >80% line coverage through extensive code cleanup
• Resolved file loading bottleneck: 14x performance gain
• USB Verification IP in UVM
• Prototyped FSM, Toggle, and Checks coverage models which were used across VIP teams.
• Restructured USB 3.X sequence collection reducing code by 25K lines
• Developed functional coverage model achieving 95% coverage with optimized compile/runtime performance
• Managed team of 4 engineers

Sep 2011 – May 2015 · 3 yrs 8 mos

• USB Test Suite in UVM
• Developed SV device driver for Synopsys USB Device RTL controller with UVM RAL integration, interrupt handling, and TRB setup
• Created comprehensive UVM test suite integrating USB Host VIP with Device RTL, including scoreboard, passive monitor, system checks, and application environment
• Published paper at SNUG Taiwan 2015 on USB test suite impact
• Restructured USB 2.0 sequence collection, reducing codebase from 25K to 2K lines and consolidating 1000 test files to 40
• Managed team of 4 engineers
• Ethernet Verification IP in UVM
• Created methodology-independent SV wrapper connecting Ethernet VIP (Verilog) with UVM, OVM, and VMM environments
• Developed comprehensive UVM components: Agent, Driver, Checks, Scoreboards
• Prototyped functional coverage model for Ethernet VIP in UVM
• Developed functional coverage for IEEE 802.3 FEC (Clause 74), XAUI (Clauses 47/48), RS-FEC (Clause 91), AN (Clause 73), and proprietary standards (Cisco SGMII, QSGMII, USXGMII, Marvell RXAUI)
• Achieved 100% functional coverage through constrained random verification
• Designed unified tiered messaging model across Ethernet VIP in UVM, OVM, and Verilog
• Deployed Ethernet VIP at 12+ customers
• Ethernet Verification IP in Verilog
• Developed Bus functional module with error injection capabilities, Checker, and Monitor in Verilog for IEEE 802.3 Ethernet Clause and proprietary Ethernet standards.
• Development done for IEEE 802.3 Forward Error Correction (FEC) Clause 74 for 10, 40, and 100G Base R models, AN Clause 73, XAUI Clause 47 and 48, Reed Solomon Forward Error Correction Clause 91, Cisco SGMII, QSGMII, USGMII, and USXGMII
• Created comprehensive test plans and coded 1000+ tests (basic, error, UNH) achieving >95% functional