Kashish M.

Product Manager

Noida, Uttar Pradesh, India9 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 4 years of experience in Verification IP Development.
Expertise in Ethernet and Interlaken protocols.
Proficient in UVM and SystemVerilog.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in IP development and testing.

Contact

Skills

Core Skills

Verification Ip DevelopmentAssertions DevelopmentUniversal Verification Methodology

Other Skills

Assertion Based VerificationC (Programming Language)Customer InteractionDesign Verification TestingEthernet VerificationFast EthernetFunctional Coverage PlanFunctional Test PlansFunctional VerificationInterlaken VerificationLinuxMicrosoft OfficePresentation SkillsQuesta Verification IPQuestaSim

About

Experienced Verification Engineer with more than 4 years of professional experience in Verification IP Development. Strong engineering professional with a Bachelor's degree (B.E. Hons) focused in Electrical and Electronics Engineering from Birla Institute of Technology and Science, Pilani. I am hard working and a quick learner. I am always trying to seek opportunities to explore new areas that are beneficial for me. Brief Summary of Experience: - Development and Verification of Ethernet (10M to 400G) and Interlaken Verification IPs. - Constrained-Random and Coverage Driven Verification. - Development and Coding of Functional Test plans and test cases. - Created Test plan and did Coverage closure for the same. - Wrote constrain random tests, ran regressions and did coverage-hole analysis. - Assertion-based Verification. - Generated directed and random test cases and debugging failure cases. Specialties: - Popular Standard Protocols: Ethernet(10M to 400G), Interlaken - Languages: SystemVerilog , C/C++ (Basics). - Verification Methodologies: UVM - Simulation & Debug Tools: Mentor (Questa) , Cadence (IUS) -Version Control: Perforce - Other Skills: LINUX

Experience

Cadence design systems

Lead Design Engineer

Apr 2022 – Present · 3 yrs 11 mos · Noida, Uttar Pradesh, India

Memory Controller IP Verification (DDR/LPDDR)

Amd

Senior Design Engineer I

Jan 2021 – Mar 2022 · 1 yr 2 mos

Design IP Verification Role

Mentor graphics

2 roles

Senior Member Of Technical Staff

Promoted

Dec 2018 – Dec 2020 · 2 yrs · Noida Area, India

Part of Mentor's Verification IP team.
Development and Verification of Ethernet (10M to 400G) and Interlaken Verification IPs for latest specifications/drafts.
Development of Assertions for Verification IP.
Development and Implementation of Functional coverage plan as per given specifications.
Development and Coding of Functional Test plans and test cases.
Interacting with customers for resolving issues and providing custom/user specific enhancements

Ethernet VerificationInterlaken VerificationAssertions DevelopmentFunctional Coverage PlanFunctional Test PlansCustomer Interaction+1

Member Technical Staff

Jul 2017 – Dec 2018 · 1 yr 5 mos · Noida Area, India

Nvidia

Engineer Internship

Jan 2017 – Jun 2017 · 5 mos · Bengaluru Area, India

Wrote a UVM Test Bench with coverage which also includes DUT in System Verilog for basic memory model.
Developing a flow for tracking and maintaining TODOs/FIXMEs in RTL and TB.
Gained hands-on-experience on Universal Verification methodology.

UVM Test BenchSystem VerilogRTL MaintenanceUniversal Verification Methodology

Birla institute of technology and science, pilani

3 roles

Laboratory Teaching Assistant

Aug 2016 – Dec 2016 · 4 mos · Chirawa Area, India

Conducted practical labs and demo session to get hands on experience on tool Cadence Virtuoso.

Laboratory Teaching Assistant

Jan 2016 – May 2016 · 4 mos · Chirawa Area, India

Arranged three practice sessions throughout the semester in the VLSI lab to assist the students with assignments and LTSpice online test and conducted weekly tutorial-cum-problem solving sessions and helped the instructor in-charge in conducting and preparing questions for the online tests.

Instructor Teaching Assistant

Jan 2016 – May 2016 · 4 mos · Chirawa Area, India

Prepared teaching material and instructions file to get hands on experience on simulation software LTSpice, conducted two lecture sessions on this tool for approximately 850 students (First year) and prepared 20 questions for the evaluation.

Putzmeister concrete machine pvt.ltd.

Student Internship

May 2014 – Jul 2014 · 2 mos · Madgaon Area, India

The project titled Analysis of Electric Controls in Putzmiester Concrete Pumps was aimed at studying wiring and testing of Concrete machines and different ways of recycling waste water used in the testing area of the machines to prepare a detailed report on the same.