Navnish Kumar

Product Manager

Noida, Uttar Pradesh, India13 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in transactor development for emulation platforms.
Led a team of engineers in advanced verification methodologies.
Extensive experience with multiple bus protocols.

Stackforce AI infers this person is a Semiconductor Verification Expert with a focus on Emulation and Transactor Development.

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Skills

Core Skills

Transactor DevelopmentEmulation PlatformsVerification

Other Skills

C++VerilogSystemVerilogUVMVAMSPerlCAlgorithmsRTL designVerilog-AMSFunctional Verification

About

As a RnD manager in Synopsys Emulation verification model development team, I lead a team of talented engineers working on various bus protocols. I have extensive experience on Zebu transactors development and have good exposure on customer testbench methodologies as well. In past, worked on multiple protocols including DDR Phys, Uart, DSI, SATA, JESD204, AVSBUS, Soundwire, SAS, Ethernet, CAN. My team specializes in simulation, emulation and hybrid verification flows. I am actively looking for passionate verification/design engineers in transactor development and customer deployment role. We have a very strong team of RTL, Verification and software engineers working on latest and upcoming emulation solutions. If you find our team interesting, contact me and we can discuss in more detail.

Experience

13 yrs 5 mos

Total Experience

3 yrs 8 mos

Average Tenure

10 yrs

Current Experience

Synopsys inc

6 roles

Sr Manager R&D

Promoted

Feb 2025 – Present · 1 yr 2 mos

> Leading a team of 7 members.
> Working on Transactor development and deployment for Emulation platforms.
> Using C++, Verilog, SystemVerilog/UVM.
> Protocols: UART, MIPI-DSI, JESD204, AVSBUS, Soundwire, CAN_FD, EtherAVB/TSN, SATA, SAS, USB
> Worked on SoC level emulation setups.

C++VerilogSystemVerilogUVMTransactor DevelopmentEmulation Platforms

R&D Manager

May 2022 – Feb 2025 · 2 yrs 9 mos

RnD Manager 1

Promoted

Feb 2021 – Apr 2022 · 1 yr 2 mos

Sr 2 RnD Engineer

Jun 2019 – Jan 2021 · 1 yr 7 mos

Sr 1 RnD Engineer

Promoted

Nov 2016 – Jun 2019 · 2 yrs 7 mos

RnD 2 Engineer

Feb 2016 – Nov 2016 · 9 mos

Juniper networks

Verification Engineer

Apr 2015 – Feb 2016 · 10 mos · Bengaluru Area, India

Worked on verification of networking related IPs using SystemVerilog and UVM.

SystemVerilogUVMVerification

Amd

Verification Engineer(contractor)

Sep 2013 – Mar 2015 · 1 yr 6 mos · Bengaluru Area, India

Worked on HBMPHY verification using UVM. HBMPHY is a DDR Phy for very high data transfer rate at comparatively lesser frequency.
Worked in a analog-mixed signal design verification using VAMS and UVM (functional, gates and co-sim verification).
Working in a C++ project using Verific HDL parser/elaborator. Verific provides the data structure of HDL code, which is accessible through C++ and Perl APIs.

UVMVAMSC++PerlVerification