Vidhu Joshi

Software Engineer

Bengaluru, Karnataka, India12 yrs 4 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Decade of experience at AMD in semiconductor design.
Authored four technical publications showcasing thought leadership.
Recipient of RTG Next 5% Award for automated regression flow.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in power management and verification.

Contact

vidhujoshi90@gmail.com LinkedIn

Skills

Core Skills

Power ManagementRtl Power AnalysisFormal VerificationTiming ClosureImplementation MethodologyPower Analysis

Other Skills

AwkClock Tree SynthesisConference SpeakingConstraint AnalysisConstraints developmentCross-functional Team LeadershipMentoringPerlPhysical DesignPlace and RoutePower MonitorPower artistRTL to GDSIIRedhawkStatic Timing Analysis

About

With a decade of experience at AMD, I have established myself as a key player in my team and working as Sr. Member of Technical Staff, contributing to critical projects such as Power signoff, RTL power management, constraints validation, and the development of verification flows. An active participant in both internal and EDA conferences, sharing my knowledge and expertise with the broader engineering community. I have also authored four technical publications, showcasing my commitment to innovation and thought leadership in the field. I graduated from Rajasthan Technical University with a Bachelor of Technology degree in Electronics and Communications Engineering, laying a strong admiration for successful career in technology. I am passionate about my work and the advancements in the field and continue to push boundaries and drive progress at my work.

Experience

Amd

6 roles

Senior Member of Technical Staff

Promoted

Jul 2025 – Present · 8 mos

Member Of Technical Staff

Aug 2022 – Jun 2025 · 2 yrs 10 mos

▪ Leading RTL, full chip and Gate level Power analysis flow deployments and support, using industry standard EDA tools for complex designs.
▪ Executing with excellence and delivering on commitments
▪ Soc Constraint generation, verification, promotion and demotion.
▪, IP and blocks Constraints generation, verification, promotion and demotion
▪ Formal Verification for blocks and Chip level using at RTL level for lower nodes
▪ Authored four technical publications, demonstrating commitment to innovation and thought leadership in the field.

Cross-functional Team LeadershipConstraint AnalysisPower managementConference SpeakingPower AnalysisRTL power analysis+2

Senior Silicon design Engineer

Promoted

Sep 2018 – Jul 2022 · 3 yrs 10 mos

▪ Deployment and Enhancement work to achieve reliable results
▪ Formal Verification for blocks and Chip level using at RTL level for lower nodes
▪ Developed a sustainable model to test and analysis Power and track for various projects as per different simulation patterns, In-short a platform dashboard to track RTL/Gate level power details for all Ips/Socs/Core globally across the different technologies.
▪ Project CAC reduction team, Infrastructure ownership of Power flows
▪ RTG Next 5% Award for Automated regression flow with common Fast Power flow internally. announced by CEO (The only member to get it from global Team)

Formal VerificationTeamworkPower management

CAD Design Engineer 2

Promoted

Dec 2015 – Aug 2018 · 2 yrs 8 mos

▪ Developed methodology for Firewall signal distribution check using industry standard tools – an Efficient way to ensure coverage of Voltage Domain Crossing Components & Internal flows management /resolving issues for the same
▪ Full Chip Timing flow creation and support
▪ Significant member of Power Management and Timing team
▪ Closed timing/Power for one of the key blocks of project (14nm)

Timing ClosureStatic Timing AnalysisImplementation Methodology

CAD Design Engineer 1

Nov 2014 – Nov 2015 · 1 yr

▪ Enabled a specific flow to calculate and monitor power numbers in various projects
▪ Deployed basic power flow for IP, Block and Full chip level, that resulted in improvement in accuracy of power and which helped them to meet power budgets.
▪ Learning Full chip Timing analysis
▪ Full chip and block level Power analysis with the help of REDHAWK Tool (ANSYS)
▪ Significant member of Timing team

TeamworkPower MonitorPower Analysis

Intern

Nov 2013 – Oct 2014 · 11 mos

▪ Physical design implementation for a block (worked on 20nm project)
▪ Floor planning at block level, placement, Clock Tree Synthesis at block level and route, physical verifications, Static timing analysis
▪ Power analysis at block and Full chip level using REDHAWK tool
▪ Timing and Power Closure of a block (audio processing)

Physical Design

Einfochips

ASIC trainee

Sep 2012 – Feb 2013 · 5 mos · Ahmedabad Area, India

▪ Implemented the distance measurer using Verilog HDL independently
▪ Architected the verification environment using Verilog
▪ Verified the Each module using Verilog
▪ Physical Design implementation for block level netlist consisting of 64 hard macros and 10k leaf cells. Netlist synthesized using Synopsys 90 nm PDK.
▪ Resolving congestion around Macros, achieving acceptable IR Drop targets

Training