Jitendra Shaw

Software Engineer

Bengaluru, Karnataka, India20 yrs 3 mos experience

Highly Stable

Key Highlights

Over 15 years of experience in design verification.
Expertise in low power UPF verification and power management.
Proficient in UVM and SoC level verification.

Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in low power and SoC verification.

Contact

Skills

Core Skills

Functional VerificationUniversal Verification Methodology (uvm)System On A Chip (soc)

Other Skills

AXIPower ManagementRTL VerificationSimulationsVLSISemiconductorsApplication-Specific Integrated Circuits (ASIC)VerilogUPFCache CoherencyFormal VerificationGate Level SimulationEDADDR2DDR

About

Design Verification Engineer with more than 15 years of experience in Power Management, Low Power UPF verification, IP level Verification, SOC level verification using SV, Specman, UVM,

Experience

20 yrs 3 mos

Total Experience

3 yrs

Average Tenure

2 yrs

Current Experience

Intel corporation

SOC design verification Engineer

May 2024 – Present · 2 yrs · Bengaluru, Karnataka, India · On-site

Tessolve semiconductor pvt. ltd.

Senior Design Verification Engineer

Sep 2023 – Apr 2024 · 7 mos · Sheffield, England, United Kingdom · On-site

worked in ARM AXI VIP team as a contractor verification engineer based in Sheffield UK

AXIFunctional Verification

Intel corporation

SOC design Verification Engineer

Dec 2020 – Aug 2023 · 2 yrs 8 mos · Bengaluru, Karnataka, India · On-site

Universal Verification Methodology (UVM)Power ManagementFunctional VerificationRTL VerificationSystem on a Chip (SoC)

Amd

2 roles

Member Of Technical Staff

Jul 2017 – Nov 2020 · 3 yrs 4 mos

Working in CXL compliant UVC development.
Working in Data Fabric Power Management Verification.
Working in Data Fabric Low Power UPF verification.

Senior Design Engineer

Dec 2013 – Jun 2017 · 3 yrs 6 mos

Freescale semiconductor

Lead Design Engineer at Freescale Semiconductor

May 2008 – Nov 2013 · 5 yrs 6 mos · Noida, Uttar Pradesh, India

I have worked on low power verification of SOC using MVSIM+CPF flow.I have worked on IP level verification of Many Debug IP. I have worked on SOC level verification. I have worked on Nexus IEEE 501 verification.

Montalvo systems

Design Engineer

Oct 2007 – Apr 2008 · 6 mos · Bengaluru, Karnataka, India

I have worked on Architecture verification of Montalvo x86 processor using x86 assembly language. Wrote different system level tests for Interrupt controller in multi core enviroment.

Conexant systems

design engineer

Jul 2005 – Sep 2007 · 2 yrs 2 mos · Pune, Maharashtra, India

I have worked in Conexant systems for 2 years and 2 months. I have worked in design verification of different module like posphy, utopia and chip level verification of these modules, Jtag, Boundary scan. I have worked in gate level simulation for some modules and asssited in DDR timing simulation. I worked on DDR2 controller verification using specman and e.