Biswajit Patra

CTO

Bengaluru, Karnataka, India23 yrs 1 mo experience
Highly StableAI Enabled

Key Highlights

  • Led implementation of industry-first SOCs with 47 chiplets.
  • Pioneered chiplet-based SOC design methodologies.
  • Recognized with multiple awards for technology innovation.
Stackforce AI infers this person is a leader in semiconductor design and AI hardware development.

Contact

Skills

Core Skills

High Performance Computing (hpc)System ArchitectureSystem On A Chip (soc)Physical Design

Other Skills

2.5D/3D system-on-package (SoP)3DIC3DIC/chiplets/foveros/EMIBAI High-Performance Computing (HPC)ASICApplication-Specific Integrated Circuits (ASIC)Artificial Intelligence (AI)AutomotiveCCross-functional Team LeadershipDebuggingEDAEmbedded SystemsFPGAField-Programmable Gate Arrays (FPGA)

About

Passionate about architecting and designing cutting-edge AI High-Performance Computing (HPC) platforms, silicon technologies & design methodology development, 2.5D/3D advanced packaging, and chiplet-based product designs. Deep expertise in optimising power-performance, networking throughput, power delivery, and thermal solutions, with a strong focus on total cost of ownership (TCO) and time to market. Expertise in providing technical leadership for the successful implementation and signoff of over 100 commercially successful SOC Physical designs, for Intel and Qualcomm in segments such as smartphones, laptops, desktops, automotive, AI/ML hardware accelerators, ultralow power devices, and HPC. Demonstrated collaborative technical leadership in pioneering chiplet/foveros/3DIC-based complex SOC design, from scratch to post-silicon validation and characterization. Led the implementation of industry-first SOCs with up to 47 chiplets, employing 3DIC-based design methodologies and ensuring first-time silicon success. Technologist in SOC-Package co-optimization, integrating high-speed IPs (DDRs, Dekel, Xeon core, Atom, Arm cores), and overseeing SI/PI, power estimation, and post-silicon co-relation in over 60+ SOCs. Specialized in auto-grade silicon creation for extreme conditions, successfully developing 6 auto-grade SOCs. Led corporate-level task-forces/work-groups, collaborating with senior technical leaders to accomplish complex cross-domain activities and strategic initiatives. Served as task force chair, focusing on next-generation disaggregation technology, power delivery, power-performance optimization, and tool-flow-methodology development. Drove the development and implementation of tool flow methodologies utilizing industry-standard tools from Synopsys, Ansys, Cadence, and Mentor Graphics (Siemens) for high-quality tape-in/tape-out. Proven track record in leadership, managing direct reports and virtual teams. Passionate about developing teams from scratch, improving sustainable efficiency, fostering next-generation technical leaders, and promoting innovation. Instrumental in driving the innovation agenda for a business group of 2000+ engineers across multiple global locations. Mentor in Intel India's flagship Startup Program, providing guidance to deep technology startups. Recognized with prestigious awards for technology innovation, including the "Innovator of the Year" and "Spirit of Qualcomm" awards at Qualcomm, as well as the "Intel Achievement Award" for 3DIC/Foveros innovation at Intel.

Experience

Krutrim

Product Architect and Technologist

Jul 2023Present · 2 yrs 8 mos

  • Driving the development of a next-generation AI HPC hardware platform with a focus on TCO optimization, aimed at democratising AI for end users.
  • The platform is designed to achieve top-tier interconnect bandwidth, optimal performance per watt, cost-efficiency, and power utilization efficiency (PUE) targeting 1.04.
  • Leading the architecture and design of 2.5D/3D system-on-package (SoP) using chiplet technology to improve design yield and accelerate design cycles.
  • Spearheading the adoption of advanced silicon technologies (3nm, 2nm, and below nodes), IP development, and tool-flow design methodologies to deliver the best possible SoC power and performance with optimal cost and time to market.
AI High-Performance Computing (HPC)TCO optimization2.5D/3D system-on-package (SoP)chiplet technologysilicon technologiestool-flow design methodologies+2

Intel corporation

3 roles

Senior Principal Engineer

Apr 2020Jun 2023 · 3 yrs 2 mos

Senior Principal Engineer

Promoted

Apr 2020Apr 2020 · 0 mo

Senior Principal Engineer at Intel Corporation

Jan 2017Jun 2023 · 6 yrs 5 mos

  • Chiplet-based (3DIC) disaggregated SOC design and related design methodologies,
  • SOC physical design implementation, specializing in the development of disaggregated SOCs using advanced technologies such as 3DIC/ chiplets/ foveros/EMIB.
  • Deep knowledge of SOC power delivery and power-performance optimization, leveraging industry best practices to achieve superior results.
  • Mentoring next generation technical leaders.
  • Mentoring startup eco system through intel start up programs as mentor.
  • SOC development leader and technologist, driven by a passion for excellence and a strong focus on execution through effective teamwork.
SOC physical design implementationdisaggregated SOCs3DIC/chiplets/foveros/EMIBpower deliverypower-performance optimizationSystem on a Chip (SoC)+1

Qualcomm

Director Technology ( Principal Engineer) Qualcomm.

Jul 2005Jan 2017 · 11 yrs 6 mos

  • SOC development Leadership, SOC physical design implementation (floor planning, auto place & route, high speed clocking) and design methodologies, SOC-PKG-PCB optimization for power & performance, power delivery network design and analysis (on die: static (IR), dynamic(IR), EM, and transient, system level: transient, impedance analysis), Pre-silicon reliability in automotive grade silicon & post-silicon characterization.
SOC development leadershipSOC physical design implementationpower delivery network designautomotive grade siliconSystem on a Chip (SoC)Physical Design

Sasken

Design Engineer

Feb 2003Jul 2005 · 2 yrs 5 mos

  • RTL design, Physical design implementation
RTL designPhysical design implementationPhysical Design

Education

Indian Institute of Management Ahmedabad

Executive MBA — Senior Leadership and management

Calcutta University, Kolkata

Doctor of Philosophy - PhD — Low Power High Performance SOC Design

Indian Institute of Corporate Affairs

Independent director — Corporate affairs

University of Calcutta

M.Tech — Electronics and Communication Engineering

Michigan State University

Effective Leadership & Management

Indian Institute of Technology, Kharagpur

Drop Out — Computer Science and Engineering

Jan 2001Present

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