Krishnendu Ghosh

Product Engineer

Bengaluru, Karnataka, India14 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

15 years of experience in front end verification.
Expertise in Hardware Verification and Test Planning.
Proven track record in complex ASIC and FPGA projects.

Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in ASIC and FPGA design.

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Skills

Core Skills

Hardware VerificationTest Planning

Other Skills

SimulationsHigh Performance Computing (HPC)AMSSystemVerilogVHDLRTL designUVMDebuggingASICModelSimVLSIVerilogHardware ArchitectureTCLEmbedded Systems

About

Around 15 years of experience in front end verification(IP,Full chip,SoC,ASIC,FPGA) .Key Skills:SV-UVM, AMS(mix signal), GLS (gate level simulation), Jasper Gold (connectivity check), Power estimation report generation with Spyglass(RTL) and primetime power(netlist) flow.

Experience

Intel corporation

IP Verification Engineer

Nov 2021 – Present · 4 yrs 4 mos · Bengaluru · Hybrid

2025 March - till date
Memory subsystem verification with LPDDR5 as PHY, memory controller and memory bridge that talks to upper layer via the fabric for SoC with product target.
Integration of svt axi4 slave
Develope CFI to AXI scoreboard and connect it with CFI-AXI BFM.
Write SV assertion around CFI credit request and response
Integration of LPDDR5 memory model
. Integrate behavioural PHY for data path with Memory model till rtl phy is available
. Data path bringup with RTL phy,MC with memory model
. Create scoreboard for write to read check at CFI interface(used as end to end data sanity till memory CFI-Mem Ctrl-PHY-Memory and back to CFI)
2021 Nov - March 2025
Verification of Graphics DDR7 PHY a custom analog IP (from evolving PHY and Memory spec till silicon success Test chips.
Setting up verification environment from scratch
.Integration of memory controller BFM and Memory model with PHY interface .
Identify and create test scenario for memory through PHY.
Bring up PHY and initiatialize memory model for data transaction.
Simulate analog circuit extracted model from schematics, with functional RTL simulation.
Create and Integrate self checking BFM as MC and system PMU for low power,periodic cal,Dynamic Frequency switch handshake with PHY.
Create system level test scenario which should comply both memory protocol and system bringup flow which involves calibration of analog model, write eye and read eye training, data rate change , data traffic from memory controller till memory via phy.
Support AMS, Sub System, Full chip team identifying scenario and simulation bringup.

SimulationsHigh Performance Computing (HPC)Test PlanningHardware Verification

Ericsson

Developer ASIC Verification

Sep 2018 – Oct 2021 · 3 yrs 1 mo · Lund, Sweden

Working as Full time direct consultant.
Generate power estimation report for RTL and netlist simulation with spyglass power and primetime power tool(May 2021-till date)
Current assignment is on verification of Digital core of a Mixed Signal ASIC(ADC-DAC test chip) with single core ARM M7 as DP. SPI and UART as off chip boot interface. Main DUT involves the digcore with these SPI, UART, SYSTEM Controller (which integrates the RAM), HSIO, CCR. Analog core includes the ADC core , DAC core, PLL core and MISC. Verification extends to the integration check of the behaviour model of the analog modules with the digital core. (May 2020- till date)
Responsibilities:
i. Creating the Verification specification.
ii. Developement of different test scenario from sanity, integration, connectivity to functional.
iii. Integration, boot up scenario developement to check the ARM M7 integrity.
iv. Create FSDB dump for selected data path, to be used in power analysis.
v. Set up reggression.
vi. Toggle coverage closure for top modules.
vii. Bring up netlist simulation.
5G-Radio implementation on FPGA and it is largely based on MIMO antenna , CPRI protocol. (September 2018-April 2020)
Responsibilities:
i. Integrate IP UVC's (CPRI, DFE) in the top level environment and make necessary changes.
ii. Prepare top level test scenario.
iii. Support Lab validation by creating and running the top scenario in functional simulation, as per requirement.
iv. Make the regression set up in VMANAGER and work with Cadence AE for xcellium/incisive script support for server selection, parallel run load sharing and related stuffs.
v. Identify top level regression test scenario and prepare the VSIF.
vi. Generating RAL model.
vii. Check Jasper Connectivity.

SimulationsTest PlanningHardware Verification

Sankalp semiconductor pvt ltd

Verification Lead

Jan 2017 – Sep 2018 · 1 yr 8 mos · Bengaluru Area, India

i. Worked in SoC verification for Intel (as consultant).
ii. Worked in eDP-PHY verification for 40nm, supporting 6 bit rates. DUT involves digital
RTL,verilog model of analog block and analog schematic extracted netlist in Mix signal simulation.
iii. Worked in Cadence, Bangalore (as Consultant). Involved in Test chip GLS , test chip connectivity check in Jasper. Assertion development in ANA-DIG boundary for isolation.
Exposed to USB2 test environment(AMS) bring up ( porting existing set up)

SimulationsTest PlanningHardware VerificationAMS