Utkarsh Garg — Software Engineer

As a Physical Design Engineer, I have had the opportunity to work on TSMC and Samsung tech nodes. My experience with advanced technology nodes has allowed me to stay up-to-date with the latest technologies and methodologies in the field. My experience includes the following: - Strong hands-on experience with Physical design implementation and timing analysis on advanced technology nodes (8nm, 7nm, 5nm, 4nm, 3nm, 2nm) - Block-level and Full-chip floor-planning, FT punching and power grid planning - Experience in working with EDA tools - Innovus, Tempus (SOD), Genus - Worked closely with Static Timing Analysis (STA) teams, EM/IR, and physical sign-off teams for chip closure. - Experience with low power implementation, multiple voltage rails, UPF

Stackforce AI infers this person is a Physical Design Engineer specializing in advanced semiconductor technologies.

Location: Delhi, India

Experience: 9 yrs 7 mos