Preetham Reddy Goudelly — Product Manager

I’m a physical/digital design engineer who turns ideas into silicon. I take blocks from RTL to GDSII, with a focus on power, performance, and area (PPA). I also verify signal integrity using ANSYS HFSS to ensure that bits arrive clean in the real world. Arizona State University has provided hands-on opportunities to develop 90nm CMOS UCIe PHY Analog and 13nm digital frontends, while collaborating with PhD students on advanced circuit architectures. Contributions include designing current-mode logic dividers and building mixed-signal validation suites. Day-to-day, I work with Synopsys DC/VCS/Verdi, Cadence Innovus/Virtuoso/Spectre, and Calibre DRC/LVS, as well as Verilog/SystemVerilog and Python. I’m curious about AI‑assisted EDA, chiplets, and the move from FinFET to GAAFET. If you’re building high-performance SoCs or high-speed I/O, let’s connect and compare notes on PPA tuning, SerDes/PCS integration, or transitioning designs from RTL to reliable silicon.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in mixed-signal and analog circuit design.

Location: Tempe, Arizona, United States

Experience: 1 yr