Nov 2022 – Present · 3 yrs 6 mos · Bengaluru, Karnataka, India

Nov 2022 – Jan 2025 · 2 yrs 2 mos · Bengaluru, Karnataka, India

• Verification owner for a module that controls instruction count delivery to the ARM Cortex-X925 CPU instruction pipeline, optimizing CPU power efficiency. Conducted comprehensive testing at both the IP level using SystemVerilog-UVM and the integration level using C-based tests to configure memory-mapped system registers. Successfully drove functional coverage closure, ensuring thorough verification. Identified and reported six critical bugs across multiple projects, contributing to improved IP integration stability and performance. Verification owner for Duty Cycle Detector & Controller module which calculates duty cycle of the output clock from the clock generation module & provides a correction code to clock generation module to avoid degradation of system clock & which was thoroughly stress tested using C & UVM Sequence tests. Completed its functional coverage closure. Identified & reported four critical bugs for this IP. Worked on GLS-SDF debugging of the core-level netlist for each project. Identified & reported a bug related to non-resettable flop for an internal state register of a sub-IP which caused X propagation which was later fixed with an ECO.

Mar 2021 – Nov 2022 · 1 yr 8 mos · Bengaluru, Karnataka, India

• 1. Maintained and improved automations to run test vectors based regressions and assign debugs to team members and reduced efforts from 3+ hours per user per week down to few minutes per user per week.
• 2. Worked with Cover-group refinements and metrics generation. Created a setup which enhances the features of merge tool to merge metrics data across multiple regressions and provide analysis of the data on a daily basis.
• 3. Improved a setup's capacity by 500% and reduce the process time from 48 hours to 4 hours by working with various stakeholders and optimized the firmware command filtering algorithm to process raw firmware data into SV sequences which could further be used to test vectors to verify the functionality of the hardware description of the product.
• 4. Knowledge about the nuances of SoC Design using Verilog and Verification of RTL design using SV and UVM 1.2 TB Architecture.

Mar 2021 – Nov 2022 · 1 yr 8 mos

Mar 2021 – Oct 2022 · 1 yr 7 mos

• Created, maintained and improved automations to run regressions and assign debugs to team members on a per regression basis and consolidated the debug tracking. Improve overall productivity by 5%. Created a automation setup to merge code & functional coverage data across regressions and provide analysis of coverage metrics of the project ensuring timely coverage closure which reduced the time taken for this task by 10%. Created & optimized a filtering algorithm script to process CPP validation tests into System Verilog sequences which could further be used to generate test vectors for IP's instead of manual creation of vectors & performed verification on product UVM sequences. Created a testbench codebase parser script to check for redundant arguments passed in run commands and reports their usage which help improve Testbench code coverage by 4.5%.

Sep 2020 – Mar 2021 · 6 mos

• Learned important skills which are utilized for RTL Design Verification such as Verilog, System Verilog, UVM and Digital Electronics. IP level verification. of AHB - APB Bridge which converts the incoming AHB transaction into APB transactions using SV - UVM Testbench setup.

Aug 2020 – Mar 2021 · 7 mos