Saranga Pogula

Software Engineer

Bengaluru, Karnataka, India26 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in SoC and ASIC verification methodologies.
  • Proven leadership in technical team management.
  • Strong background in embedded systems and hardware verification.
Stackforce AI infers this person is a highly skilled ASIC and SoC verification engineer with extensive experience in hardware design and validation.

Contact

LinkedIn

Skills

Core Skills

Technical LeadershipUniversal Verification Methodology (uvm)DebuggingRtl Verification

Other Skills

System on a Chip (SoC)System ArchitectureEmbedded SystemsVerification and Validation (V&V)InterconnectTest CasesTest PlanningPCIeProblem SolvingAXIFabricsTest AutomationHardware VerificationFPGA prototypingArchitecture

About

SoC/ASIC/IP Verification

Experience

26 yrs 9 mos
Total Experience
4 yrs 5 mos
Average Tenure
14 yrs 8 mos
Current Experience

Intel corporation

2 roles

Principal Engineer

Promoted

Mar 2021 – Present · 5 yrs 1 mo

Technical LeadershipUniversal Verification Methodology (UVM)System on a Chip (SoC)System ArchitectureDebuggingEmbedded Systems+22

Sr. Technical Lead Engineer

Aug 2011 – Apr 2021 · 9 yrs 8 mos

  • Chip/IP Verification Architecture
Technical LeadershipUniversal Verification Methodology (UVM)System on a Chip (SoC)System ArchitectureDebuggingInternet Protocol Suite (TCP/IP)+23

Oracle corporation

Senior Verification Engineer

Jan 2010 – Aug 2011 · 1 yr 7 mos · Santa Clara, CA

  • ASIC Verification Lead
Technical LeadershipUniversal Verification Methodology (UVM)System on a Chip (SoC)System ArchitectureDebuggingInternet Protocol Suite (TCP/IP)+15

Sun microsystems

Staff Engineer

Jan 2005 – Dec 2009 · 4 yrs 11 mos · Santa Clara, CA

  • ASIC Verification Lead Engineer
Universal Verification Methodology (UVM)DebuggingInternet Protocol Suite (TCP/IP)Embedded SystemsVerification and Validation (V&V)RTL Verification+9

Force10 networks

ASIC Verification Engineer

Jun 2001 – Jan 2005 · 3 yrs 7 mos · Santa Clara, CA

  • ASIC Verification
DebuggingInternet Protocol Suite (TCP/IP)RTL VerificationTest CasesHardware Verification

Iready

ASIC Verification Engineer

Jun 2000 – Jun 2001 · 1 yr · Santa Clara, CA

  • ASIC Verification Engineer
Internet Protocol Suite (TCP/IP)

Aurora vlsi

Hardware Engineer

Jun 1999 – Jun 2000 · 1 yr · Santa Clara, CA

  • ASIC Verification
Verilog

Education

Indian Institute of Technology, Kharagpur

M.Tech. — Microelectronics and VLSI Design Engineering

Jan 1996 – Jan 1997

Bapatla Engineering College

B.Tech. — Electronics and Communication Engineering

Jan 1991 – Jan 1995

Bapatla College of Arts & Science

XII

Jan 1989 – Jan 1991

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