Mohit Parihar

Software Engineer

San Diego, California, United States10 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 9 years of experience in ASIC Design and Verification.
Expert in SoC Verification using UVM methodology.
Proven track record in leading verification tasks and mentoring.

Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in ASIC and SoC design.

Contact

Skills

Core Skills

Asic DesignSoc Verification

Other Skills

AMBA AHBAXICCadence EncounterCadence VirtuosoCoverageCoverage analysisDebuggingDigital ElectronicsEthernetFullchip RTL simulationsFunctional verificationGLS verificationICIntegrated Circuits (IC)

About

I am a Verification Engineer with experience of more than 9 years and currently working at Qualcomm, San Diego, California. I have done my Dual Degree (B.Tech + M.Tech) in Electrical Engineering with specialization in Microelectronics and VLSI Design from IIT Madras. You can reach me on my mail id - mohitparihar1@gmail.com 9 years of experience in ASIC Design and Verification • Experience in SoC Verification • Extensive experience in SV/UVM methodology and Verilog/C based methodology. • Experience with protocols like Ethernet and USB 2.0, AHB, AXI, SPMI VGIS (MIPI protocol). • Debugging experience in Pre and post silicon failures. • Good exposure to both RTL and GLS verification. • Low power verification of SoC, Worked on PA RTL and PA GLS. • Worked on SoC Gate Level Simulation, Xprop, SDF & Timing Debug, ATE Vector generation, Silicon bringup. • Test vector development for post silicon validation of Mobile Snapdragon chipset. • Experience in Leading Verification Task/Activities and Mentoring RCG ( recent college graduates )

Experience

Qualcomm

5 roles

Senior Staff Engineer

Promoted

Nov 2024 – Present · 1 yr 4 mos

Staff Engineer

Nov 2020 – Nov 2024 · 4 yrs

Senior Engineer

Nov 2019 – Nov 2020 · 1 yr

Senior Engineer

Promoted

Dec 2017 – Nov 2019 · 1 yr 11 mos

IP and Subsystem and SOC Level Verification:
+ Adding Environment support for new features and writing test cases to verify the new features.
+Developing Test bench setup and test plan.
+ Coverage analysis.
+ Debugging the test cases failures.
+ Worked on Fullchip RTL simulations debug, Toggle coverage.

VerificationTest bench setupCoverage analysisDebuggingFullchip RTL simulationsASIC Design+1

Engineer

Mar 2016 – Nov 2017 · 1 yr 8 mos

Done functional verification of different peripherals like Ethernet, USB along with verification of Boot Loader image.
In depth knowledge of Boot Up sequence, Coverage and Vector generation.
Skill Set & Work Exposure :
+ Good Knowledge in Verilog HDL, System Verilog.
+Worked on Test case development using System Verilog & UVM.
+ Experience in UVM based SOC verification Environment.
+ Handling GLS verification and vector delivery for Ethernet and USB.
+ Worked on Ethernet protocol & Familiar with Perl scripting.
+ developed Scoreboard development for different IPs at SoC .
+ Coverage analysis like code coverage, functional coverage.
+ Coding experience in C, Verilog
+ Worked on Synthesizable CRC Generator by using C language.
+ Indepth understanding of Pipelining & Good knowledge on Computer Architecture.
+ Exposure to VCS, Modelsim.

Functional verificationTest case developmentUVMGLS verificationCoverage analysisSoC Verification+1

Indian institute of technology, madras

Teaching Assistant

Jun 2013 – May 2014 · 11 mos · Greater Chennai Area

+Mentored students carrying out experiments on Spartan 3E FPGA starter kit, blackfin processor and ARM microprocessor.
+Conducted tutorial sessions on Computer Organization and Architecture course.
+Helped students master the course by catering to their questions and discussing important concepts like cache, pipelining, memory organization etc.

Cadence design systems

Intern

May 2012 – Jul 2012 · 2 mos · Noida, Uttar Pradesh, India

+Implemented synthesizable CRC generator.
+Synthesizable Verilog code which calculates the CRC Checksum of given data efficiently by using look up tables.
+Generated look up tables for reading the data file in pdh form and calculating the CRC for the given data using C.
+Supported CRC types of 3 bit, 16bit, 32bit, 64 bit.
Skills used:
Verilog, C