Rashmi Soni

Software Engineer

Bengaluru, Karnataka, India11 yrs 9 mos experience

Most Likely To Switch

Key Highlights

6+ years in Physical Design Engineering
Expert in Netlist2GDSII flow and Signoff Verification
Proven track record in deep submicron technology projects

Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in VLSI and ASIC design.

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Skills

Core Skills

Physical DesignVlsi

Other Skills

ASIC Physical Design flowCTSECO generationFloor planningLinuxLow-power DesignPlacementRoutingSignoff verification checksStatic Timing AnalysisTiming closureVerilog

About

Enthusiastic and skilled Physical Design Engineer with 6+ experience in the domain; Well versed in Netlist2GDSII flow including Signoff Verification checks; Collaborated in different projects for leading Semiconductor ventures in deep submicron technology

Experience

Synopsys inc

Staff Engineer, Application Engineering

May 2023 – Present · 2 yrs 10 mos · Bengaluru, Karnataka, India · Hybrid

Collaborating with customers in providing Fusion Compiler tool debug support.

Cadence design systems

Design Engineer II

Oct 2021 – May 2023 · 1 yr 7 mos · Bengaluru, Karnataka, India · Hybrid

Working on implementation of block level PnR and all the signoff checks - DRC, LVS, IR, Antenna. Working on fixing read and write skews, duty cycle distortion, max trans-max cap violations and implemented timing ECOs.

Hcl technologies

Physical Design Engineer

Feb 2019 – Oct 2021 · 2 yrs 8 mos · India

Working on ASIC Physical Design flow (RTL to GDS) using ICC and ICC2. Working on Floor planning, Placement, CTS, Routing, ECO generation , Signoff verification checks and timing closure for block level designs. Working on issues related to Congestion, multiple macro placement, Clock Tree designing , IO placement, Timing, EM and IR drop.
Handling high complex chips with challenges in achieving the optimal QoR. Leveraging the PnR tool capabilities to achieve the design closure and meeting the customers challenging delivery schedule

Physical DesignASIC Physical Design flowFloor planningPlacementCTSRouting+4

Rv vlsi design centre

Physical Design Trainee

May 2018 – Feb 2019 · 9 mos

Implementation of Block-level Physical Design through PnR flow.Worked on Floorplan, Place and Route, CTS, Extraction, STA and Verification checks (DRC, LVS, LEC, IR, EM)

Intel corporation (formerly soft machines inc.)

2 roles

Post-Silicon Validation Egineer

Apr 2017 – Apr 2018 · 1 yr · Bengaluru, Karnataka, India

Working on graphics processor post silicon validation. Capturing the FPS and bandwidth data for different configurations like memory scaling, GT frequency scaling and performance evaluation. Post-Silicon GPU Performance measurement, debug and analysis for PnP Projection with industry wide benchmarks. Power & Performance miscorrelation and anomaly debug with DX/ OGL/ OpenCL workloads at application/ driver/ hardware level

CPU Verification Engineer

Feb 2013 – Jan 2016 · 2 yrs 11 mos · Greater Hyderabad Area

Performed verification operations on Processor Architecture wherein the work included generating sequence of Instructions, looking for Instruction Scheduling and Execution in the Pipeline followed by Verifying and Debugging the results and Reporting the RTL bugs to the Design team