Manan Chugh

DevOps Engineer

Austin, Texas, United States11 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in performance modelling and verification.
Developed innovative tools for performance analysis.
Awarded for contributions to SPARC processors.

Stackforce AI infers this person is a Semiconductor Architect with expertise in performance modelling and verification.

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Skills

Core Skills

Performance ModellingPerformance VerificationPerformance CorrelationPerformance AnalysisFunctional VerificationGraphics DesignVerification

Other Skills

3D Graphics IP designCC++CUDACadence VirtuosoComputer ArchitectureData StructuresDigital ElectronicsEagleElectronicsFPGAField-Programmable Gate Arrays (FPGA)IBM High Availability Cluster Multiprocessing (HACMP)ICIntegrated Circuit Design

About

Interested in Computer Architecture. Performance-modelling at Arm. Prior industry work-experience in Performance-modelling and correlation at Samsung Austin R&D Centre; Performance Analysis at Oracle; in Functional Verification with Synopsys Inc.; as well as front-end development of 3D Graphics IP blocks as Graphics RTL Design Intern at Intel Corporation. Specialties: • Languages: Python, C, C++ and Data Structures, System Verilog, Verilog, VHDL, MATLAB • Programming Standards: -- Python: Pexpect, Multiprocessing, Scikit-Learn, Numpy, Matplotlib. -- Verification: UVM -- Programming: CUDA, MPI, Pthreads, OpenGL. • Tools: Sun Studio’s Performance Analyzer, Synopsys’ VCS, Verdi, Cadence Virtuoso, Design Compiler; Xilinx Vivado HLS; ORCAD PSPICE; Mentor Graphics’ ModelSim; Mentor Graphics' Precision RTL; EAGLE PCB Design • Version control tools: Perforce, Git.

Experience

11 yrs 2 mos

Total Experience

2 yrs 3 mos

Average Tenure

3 yrs 10 mos

Current Experience

Arm

Staff Engineer - Performance Modelling

Jun 2022 – Present · 3 yrs 10 mos

Samsung sarc | acl

2 roles

Senior Performance Architect - SoC Memory

Promoted

Mar 2018 – Jun 2022 · 4 yrs 3 mos

Ownership of performance modelling, performance correlation and performance verification of next-gen Samsung memory controllers for LPDDR4 and LPDDR5.
Active member of ‘Microarchitecture Think-Tank’ responsible for novel ideas to improve performance and power. Responsible for multiple feature-suggestions that have made Plan-of-Record.
Single-handedly achieved all correlation targets within 8 months of launching correlation effort.
Architected and developed ‘SMC-Cmd-Log-Parser’ to accelerate performance correlation by comparing DRAM command-scheduling between RTL and Performance Model. Implemented using Python.
Architected and developed the tool ‘Spa-Bisect’ to pin-point the exact commit that moved performance, implemented using Python. Integrated with regression-framework to remove any user-intervention.

Performance modellingPerformance correlationPerformance verificationPython

Performance Architect - CPU

Nov 2017 – Feb 2018 · 3 mos

Performance correlation between RTL and performance model for next-gen Samsung CPUs.
Developed ‘anti-preloading’, a framework to force cache-evictions for analyzing power-consumption along the cache-hierarchy, implemented using Python.

Performance correlationPython

Oracle

Hardware Developer - Empirical Analysis

Jun 2016 – Oct 2017 · 1 yr 4 mos · Santa Clara, California

Performance analysis, verification and validation of Data Analytics Accelerator (DAX) engines on FPGA-based emulation platform, for next-gen SPARC processors.
Develop and optimize Oracle Database by adding support for SQL query execution on DAX.
Architected and developed the complete regression test-suite for functional verification of query execution on DAX, implemented using Python. Awarded with “SPARC Processors Achievement Award” for this effort.

Performance analysisVerificationPython

Intel corporation

Graphics RTL Design Intern

May 2015 – Nov 2015 · 6 mos · Folsom, CA

Front-End Development - design and validation - of 3D Graphics IP blocks for Intel’s next-gen processors.
Primary designer and joint-owner in creation and development of a new ‘Coverage-Analytics’ application for interactive analysis of input vectors in testbenches, implemented using Python.

3D Graphics IP designPythonGraphics design

Synopsys

R&D Engineer - Verification IP

Jul 2013 – Jul 2014 · 1 yr · Noida Area, India

Design of Verification IP of HDMI 2.0 protocol (with support of HDCP 1.4 and HDCP 2.2 encryption protocols) in SystemVerilog (architected with native support for UVM).
Held the ownership for the Display Data Channel (DDC) in HDMI, along with partial ownership of the TMDS channel. Major contributor in the overall improvement of Synopsys’ HDMI 2.0 VIP during my tenure.
Awarded “Team Excellence Award” for successful engagement with a major semiconductor firm.

Verification IP designSystemVerilogUVMVerification

Mentor graphics

Intern

Jun 2012 – Jul 2012 · 1 mo · Noida Area, India

Summer Intern in Design Creation and Synthesis Group (Product Engineering).
Verification of the FPGA synthesis and PnR tool "Precision RTL Plus Synthesis".
Achieved through automated “simulation-comparison” between RTL and netlists generated after synthesis and PnR.