Akhil Arora

Software Engineer

India17 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in SoC verification methodologies.
Proven leadership in low power verification.
Extensive experience with emulation platforms.

Stackforce AI infers this person is a seasoned expert in semiconductor design and verification, specializing in SoC and emulation technologies.

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Skills

Core Skills

Soc VerificationVerification MethodologiesVeloce EmulationSystem Verilog Design And VerificationTechnical Support

Other Skills

SystemVerilogPerformance verificationvalidationRTL CodingUniversal Verification Methodology (UVM)VELOCEUPFLow Power VerificationSimulationsCadenceC++Requirements AnalysisIntegrationHardware Description LanguageEDA

Experience

17 yrs 9 mos

Total Experience

5 yrs 11 mos

Average Tenure

8 yrs 3 mos

Current Experience

Qualcomm

2 roles

Senior Staff Engineer

Promoted

Dec 2021 – Present · 4 yrs 4 mos

SoC Verification lead with expertise in Verification methodologies, Low power, Emulation

SystemVerilogPerformance verificationvalidationSoC VerificationVerification methodologies

Staff Engineer

Jan 2018 – Apr 2023 · 5 yrs 3 mos

SoC verification

SoC verification

Mentor graphics

Lead Member Technical Staff

Feb 2014 – Jan 2018 · 3 yrs 11 mos · Noida Area, India

Customer support and Deployment engineer for Veloce Emulation platform
ICE/TBX envs

Veloce Emulation

Cadence design systems

2 roles

Senior Support Application Engineer

Promoted

Jul 2008 – Feb 2014 · 5 yrs 7 mos

Incisive Unified Simulator
Incisive Comprehensive coverage
System Verilog Design and Verification
System Verilog Assertions
c
c++
TCL

System Verilog Design and Verification

Support Application Engineer

Jul 2008 – Mar 2010 · 1 yr 8 mos

Providing Technical Support for Cadence Incisive Platform tools:
o Incisive Unified Simulator (IUS)
o Incisive Comprehensive Coverage
o HDL analysis and Lint (HAL)
Resposible for working with customers and providing technical assistance to resolve issues/problems during the design and verification cycle.
Analyzing requirements, designing solutions, troubleshooting for complex issues related to various aspects of HDLs, HVL and the tools.
Mapping business requirements and providing hardware/applications solutions involving selection of appropriate techniques.
Acting as an interface between the Cadence R&D team and the customers, playing major role of providing feedback to R&D, hence contributing in enhancing the tool quality and feature-set.
Creating test cases in HDLs and HVLs such as VHDL, Verilog and System Verilog to define the use model for users.
Conducting system study and coordinating with team members for System Design & Integration, Application Maintenance.
Creating quality solutions and application notes to enhance the product knowledge database.

Technical Support