Marc Vaz

CTO

Santa Clara, California, United States17 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in GPU architecture and performance optimization.
Led significant validation improvements in semiconductor design.
Strong background in avionics and embedded systems.

Stackforce AI infers this person is a Semiconductor and Aerospace expert with strong skills in performance optimization and validation.

Contact

Skills

Core Skills

Performance AnalysisC++Performance VerificationArchitectural ModelingFpgaCo-processor MonitoringUnit TestingIntegration Testing

Other Skills

AeronauticsArchitectural FeaturesAutomation ToolsAvionicsCCollaborationComputer ArchitectureDO-178BDebuggingDesign Space ExplorationEmbedded SoftwareEngineeringField-Programmable Gate Arrays (FPGA)MatlabOperating Systems

Experience

Nvidia

2 roles

Senior GPU architect

Promoted

Mar 2015 – Present · 11 yrs

SM application performance lead for our new architectures.
Implement new architectural features in the C++ performance/timing simulator for analysis.
Working on optimizing the performance of Ray Tracing and Tensor cores.
Analysis and optimization of graphics and compute applications for new architectures.
Leading the SM unit level performance validation for new features through directed tests.
Working collaboratively with the ASIC/RTL team on validation and analysis of application performance in simulation, emulation and Silicon.

C++Performance AnalysisArchitectural FeaturesSimulationCollaboration

Architect - SM Performance

Feb 2013 – Mar 2015 · 2 yrs 1 mo

Responsible for modelling architectural features in the data-path, control and memory units - have a very good understanding of the entire SM.
SM Arch performance verification lead for one architecture family - wrote test plan, wrote directed tests, worked with RTL to ensure equivalence, took test plan to closure
Significantly improved a validation flow that uses a golden architectural model to verify the timing simulator and RTL based on its internal state, used for validating tough to reach architectural features.
Performance studies for different architectural features, evaluating design trade-offs, identifying performance bottlenecks
Bring-up lead for one of our chips - ensured a smooth bring-up process
Developed performance validation directed and OpenGl tests
Analyzing performance of real world workloads on the SM timing simulator, liasing with RTL to understand performance discrepancies
Worked on competitive analysis using directed testing, used directed tests to perform feature analysis, extracted perf and power numbers and analyzed them for information.

Architectural ModelingPerformance VerificationTestingValidation Flow Improvement

Cornell university

Graduate Research Assistant

Jan 2012 – Dec 2012 · 11 mos · Tompkins County, New York, United States

More information on each of these and my course projects can be found on my personal site
Evaluated different co-processor monitoring and protection schemes for the LEON3 core
Implemented a co-processor monitor to provide array bounds protection based on the HARDBOUND memory protection scheme.
Performing design space exploration of different FPGA architectures using on open source FPGA-CAD tool flow
Implemented a co-processor based tightly coupled security monitoring scheme for the LEON3 core that provides features like Memory space protection, data flow protection based on privilege, system call protection based on privilege, control transfer protection, register window protection and stack memory protection. This hardware protection schemes are intended to be used by a modified version of the RTEMS system currently under work by the University of Idaho

FPGACo-Processor MonitoringSecurity MonitoringDesign Space Exploration

Honeywell

2 roles

Senior Engineer

Aug 2008 – Aug 2011 · 3 yrs

Performed Unit and Integration testing for multiple modules of the Next Generation Flight Management System in C++, this product uses a completely new software product line approach to development and is the future of FMS
Resolved critical program level issues arising out of factors such as endian-ness, stack overflows, compiler variation, optimizations and ISA behavior on porting to a new architecture
Defined testing strategies based on NGFMS architecture and design patterns for a number of packages, resulting in considerable savings. I was also a member of the Technical Council
Led a small team of 8-10 people, responsibilities included planning, mentoring, task assignment, tracking and resolution of technical issues
Developed various automation tools automated the creation of SCRs, using IBM rational ClearQuest API
Process focal for a 40 member team, ensured adherence to quality and success in audits, trained the team and improved process. Successfully took the team through SOI3, AS9100 audits with the FAA and counterparts.

C++Unit TestingIntegration TestingAutomation Tools

Trainee Engineer

Feb 2008 – Jul 2008 · 5 mos

Trained on
C, C++ and design patterns,
Operating System programming - Unix, Windriver
Aeronautics domain training - Displays, Flight Controls, Flight Management System, Bus Architecture like the ARINC 429, CAN BUS,
Organization Process CMMI to Six Sigma, Certification Process for Avionics Software, DO178B

CC++Operating SystemsAeronautics