Nov 2020 – Mar 2022 · 1 yr 4 mos

• -- Leading a team for Low Power Verification of different individual IPs used for multiple Chipsets using standalone & Co-Verif Environment

Nov 2016 – Oct 2020 · 3 yrs 11 mos

• Worked on SoC verification for ARM processors based Server Chips(QDT). responsible for handling the Security + XPUs(Protection units) at SOC Level
• Worked on SS(NSP) Verification of Inference Chip : Involved in Creating SV/UVM TB from Scratch

Jun 2016 – Nov 2016 · 5 mos

Jun 2014 – Jun 2016 · 2 yrs

• Project:
• 1) NIC model : To generate an interconnect(NIC model) which can connect almost 69X90 master and slaves respectively from different protocols. This further involves the bridging(conversion of 1 protocol to another), arbitration, decoding & driving of different protocols to different channels. This was achieved by using UVM methodology and SV language. Automation using perl was also a part of it and different denali VIPs were modeled to integrate as masters and slaves.
• 2) SD host controller:- To develop and integrate a SD Host controller (which involve different protocols like SD/eMMC ) into an SOC environment. This was achieved using System Verilog and the verification environment was developed under C which was further used using DPIs into the SV environment. This C tests environment is then converted into UVM-Methodology and further verification of SOC is done by adding covergroups, assertions and mapping the coverage metrics to vPlan
• Experience Gained :
• Protocol - SD/eMMC, AXI, AHB, APB,
• Tool - IUS, IMC, Simvison, Pureview, Perl
• Technology- System Verilog, C-DPIs, UVM, SOC integration

Sep 2011 – Jun 2014 · 2 yrs 9 mos

• RESPONSIBILITIES:
• To verify the NCV & IUS simulator features related to coverage using CDV (Coverage Driven Verification)
• EXPERIENCED GAINED:
• Knowledge: EDA (IUS & NCV), Coverage analysis & improvement, Scripting (Shell, Perl), Verification (Verilog, System Verilog, UVM).

Dec 2010 – Sep 2011 · 9 mos · New Delhi

• RESPONSIBILITIES:
• To verify & modify the existing VIP of bus protocols (AXI, AHB, QSB-AXI) by developing verification environment using OVM methodology and Verilog.
• Coverage Enhancement using tools like Questa, VCS etc.
• Managing the team of 3 people under me
• Experience Gained:
• Verification : OVM, System-Verilog, Verilog
• Knowledge: Bus Protocols (AXI, AHB), Coverage analysis & improvement.
• Management: Time Management & Team Management.

Jun 2010 – Dec 2010 · 6 mos

• I got hands on training on System Verilog and Perl Scripting through professionals who had been in the EDA/ASIC/Embedded industry for more than 10 years in companies such as Cadence Design Systems & Patni Computers

Jan 2010 – Jun 2010 · 5 mos

• Responsibilities: To test & integrate the R&D done using the software & hardware revisions in the electronic designs. To manage & train team of 3 employees and deal with customer at times.
• Experience Gained: Embedded Software & Hardware development, Marketing & PR.