Rushikesh Shinde

Software Engineer

Taiwan9 yrs 6 mos experience

AI EnabledHighly Stable

Key Highlights

Led STA flow standardization for Snapdragon SoCs.
Developed machine learning based CAD tools for EDA.
Created automated design sign-off systems improving efficiency.

Stackforce AI infers this person is a Semiconductor Engineering Expert with a focus on EDA and DFT methodologies.

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Skills

Core Skills

Static Timing AnalysisMachine LearningDftLogic Equivalence CheckingPythonAutomation

Other Skills

AIASP.NETArtificial Intelligence (AI)Automated Design Sign-off SystemAutomatic Test Pattern Generation (ATPG)CC++Cadence VirtuosoComputer-Aided Design (CAD)Design Yield ScorerEDAEquivalence CheckingFormal VerificationFunctional VerificationGraphical User Interface (GUI)

Experience

Qualcomm

Senior Engineer

Dec 2024 – Present · 1 yr 3 mos · Ireland, Europe

Lead engineer for STA flow; standardizing reference flow used across all Snapdragon SoCs for both block level and full chip level.
Specialized in developing machine learning based CAD tools with automated STA and DFT setup, diagnostics, and report generation.
Driving STA QoR improvements by building automated timing regression dashboards and critical path analysis, improving timing debug efficiency by 40% across N3/N2 design blocks.
Consulting on LEC issues resolution for Formality and Conformal.
Collaborating with EDA tool vendors, Synopsys, and Cadence to resolve critical tool issues, improving efficiency.
Exploring use of AI agents to build more robust and AI enabled in-house EDA toolset.

Static Timing AnalysisMachine LearningDFTEDAPythonAI

Tsmc

Senior Engineer

Aug 2020 – Nov 2024 · 4 yrs 3 mos · Hsinchu City, Taiwan

Developed DFT and timing methodologies for CPU and GPU chips across advanced nodes, improving testing and sign-off workflows.
Owned Logic Equivalence Checking flow, supporting 12+ tape-outs at cutting-edge process nodes (N4, N3, N2, A14, 3D Fabric).
Helped enabling IEEE 1838-based 3D DFT flow in collaboration with Cadence for stacked chips. Implemented IJTAG scan insertion and pattern generation for stuck/transition/bridge models for TSMC test chips based on 4nm, 3nm process.
Design Yield Scorer (DFX): Designed a Python-based design scoring system to evaluate 50+ design-based parameters for yield, reliability, and testability impact, adopted by cross-functional teams to drive yield-aware design reviews.
Automated Design Sign-off System (Asic QC): Created a signoff automation platform covering 8 front-end quality checks (DV, VCLP, SPYGLASS, TMAX, ATPG), reducing manual effort by 8x and QC debug time by 20x.
Inter-Metal Bridge Methodology (PD & DFT): Developed novel methodology to extract inter-metal bridge sites from physical design database and generate dynamic bridging patterns, boosting hotspot detection 50% and defect detection 20%.

DFTLogic Equivalence CheckingPythonDesign Yield ScorerAutomated Design Sign-off System